IS64LP12832-166BA1 datasheet, PDF

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IS64LP12832-166BA1: DescriptionCache SRAM, 128KX32, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119; Categorystorage; File Size120KB，17 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS64LP12832-166BA1 Overview

Cache SRAM, 128KX32, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119

IS64LP12832-166BA1 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	PLASTIC, BGA-119
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	4194304 bit
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX32
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	2.41 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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IS64LP12832

IS64LP12836, IS64LP25618

128K x 32, 128K x 36, 256K x 18

SYNCHRONOUS

PIPELINED STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Interleaved or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Power-down snooze mode

• Power Supply

+ 3.3V V

+ 3.3V OR 2.5V V

DDQ

(I/O)

• Temperature offerings

Option A1: -40

C to +85

Option A2: -40

C to +105

Option A3: -40

C to +125

ISSI

ADVANCED INFORMATION

JANUARY 2003

DESCRIPTION

The

ISSI

IS64LP12832, IS64LP12836, and IS64LP25618

are high-speed synchronous static RAMs designed to

provide high-performance memory with burst for high-

speed networking and communication applications.

IS64LP12832 is organized as 131,072 words by 32 bits.

IS64LP12836 is organized as 131,072 words by 36 bits.

IS64LP25618 is organized as 262,144 words by 18 bits. The

IS64LP12832, IS64LP12836, and IS64LP25618 are fabri-

cated with

ISSI

's advanced CMOS technology. These

devices integrate a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single mono-

lithic circuit. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be from

one to four bytes wide as controlled by the write control

inputs.

Separate byte enables allow individual bytes to be written.

BW1

controls DQa,

BW2

controls DQb,

BW3

controls

DQc,

BW4

controls DQd, conditioned by

BWE

being

LOW. A LOW on

input would cause all bytes to be

written.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-166

3.5

166

-150

3.8

6.7

150

Units

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the

latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

01/20/03

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