Maximum Junction Temperature (Plastic Packages) . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 30mA for maximum reliability.
Electrical Specifications
V
SUPPLY
=
±5V,
A
V
= +1, R
L
= 100Ω, Unless Otherwise Specified
TEST
CONDITIONS
(NOTE 3)
TEST
LEVEL
TEMP.
(
o
C)
PARAMETER
INPUT CHARACTERISTICS
Output Offset Voltage
MIN
TYP
MAX
UNITS
A
A
25
Full
Full
25
85
-40
25
85
-40
25
Full
Full
25
Full
25
85
-40
25
25
25, 85
-40
25
25
-
-
-
42
40
40
45
43
43
-
-
-
-
-
0.8
0.5
0.5
280
-
±1.8
±1.2
-
-
2
3
22
45
44
45
49
48
48
1
3
30
0.5
-
1.1
1.4
1.3
350
1.6
±2.4
±1.7
7
3.6
10
15
70
-
-
-
-
-
-
15
25
80
1
3
-
-
-
420
-
-
-
-
-
mV
mV
μV/
o
C
dB
dB
dB
dB
dB
dB
μA
μA
nA/
o
C
μA/V
μA/V
MΩ
MΩ
MΩ
Ω
pF
V
V
nV/√Hz
pA/√Hz
Average Output Offset Voltage Drift
Common-Mode Rejection Ratio
ΔV
CM
=
±1.8V
ΔV
CM
=
±1.8V
ΔV
CM
=
±1.2V
Power Supply Rejection Ratio
ΔV
PS
=
±1.8V
ΔV
PS
=
±1.8V
ΔV
PS
=
±1.2V
Non-Inverting Input Bias Current
B
A
A
A
A
A
A
A
A
Non-Inverting Input Bias Current Drift
Non-Inverting Input Bias Current Power
Supply Sensitivity
Non-Inverting Input Resistance
ΔV
PS
=
±1.25V
B
A
A
ΔV
CM
=
±1.8V
ΔV
CM
=
±1.8V
ΔV
CM
=
±1.2V
A
A
A
C
C
A
A
f = 100kHz
f = 100kHz
B
B
Inverting Input Resistance
Input Capacitance
Input Voltage Common Mode Range
(Implied by V
IO
CMRR and +R
IN
Tests)
Input Noise Voltage Density (Note 4)
Non-Inverting Input Noise Current Density
(Note 4)
2
HFA1115
Electrical Specifications
V
SUPPLY
=
±5V,
A
V
= +1, R
L
= 100Ω, Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
(NOTE 3)
TEST
LEVEL
TEMP.
(
o
C)
PARAMETER
TRANSFER CHARACTERISTICS
Gain
MIN
TYP
MAX
UNITS
A
V
= -1
A
A
25
Full
25
Full
25
Full
-0.98
-0.975
0.98
0.975
1.96
1.95
-0.996
-1.000
0.992
0.993
1.988
1.990
-1.02
-1.025
1.02
1.025
2.04
2.05
V/V
V/V
V/V
V/V
V/V
V/V
A
V
= +1
A
A
A
V
= +2
A
A
AC CHARACTERISTICS
-3dB Bandwidth
(V
OUT
= 0.2V
P-P
, Note 4)
A
V
= -1
A
V
= +1, +R
S
= 620Ω
A
V
= +2
Full Power Bandwidth
(V
OUT
= 5V
P-P
at A
V
= +2/-1,
4V
P-P
at A
V
= +1, Note 4)
Gain Flatness
(to 25MHz, V
OUT
= 0.2V
P-P
, Note 4)
Gain Flatness
(to 50MHz, V
OUT
= 0.2V
P-P
, Note 4)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 4)
A
V
= -1, R
L
= 100Ω
A
A
Output Current (Note 4)
A
V
= -1, R
L
= 50Ω
A
A
Output Short Circuit Current
Output Resistance (Note 4)
Second Harmonic Distortion
(A
V
= +2, V
OUT
= 2V
P-P
)
Third Harmonic Distortion
(A
V
= +2, V
OUT
= 2V
P-P
)
DC, A
V
= +2
10MHz
20MHz
10MHz
20MHz
B
B
B
B
B
B
25
Full
25, 85
-40
25
25
25
25
25
25
±3.0
±2.8
50
28
-
-
-
-
-
-
±3.2
±3.0
55
42
90
0.07
-50
-45
-50
-45
-
-
-
-
-
-
-
-
-
-
V
V
mA
mA
mA
Ω
dBc
dBc
dBc
dBc
A
V
= -1
A
V
= +1, +R
S
= 620Ω
A
V
= +2
A
V
= +1, +R
S
= 620Ω
A
V
= +2
A
V
= +1, +R
S
= 620Ω
A
V
= +2
B
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
225
200
225
157
140
125
±0.1
±0.04
±0.25
±0.1
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
dB
dB
dB
dB
TRANSIENT RESPONSE
A
V
= +2, Unless Otherwise Specified
Rise and Fall Times
(V
OUT
= 0.5V
P-P
, Note 4)
Overshoot
(V
OUT
= 0.5V
P-P
, V
IN
t
RISE
= 2.5ns)
Slew Rate
(V
OUT
= 5V
P-P
, A
V
= -1)
Slew Rate
(V
OUT
= 4V
P-P
, A
V
= +1, +R
S
= 620Ω)
Rise Time
Fall Time
+OS
-OS
+SR
-SR (Note 5)
+SR
-SR (Note 5)
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
1.7
1.9
0
0
1660
1135
1125
800
-
-
-
-
-
-
-
-
ns
ns
%
%
V/μs
V/μs
V/μs
V/μs
3
HFA1115
Electrical Specifications
V
SUPPLY
=
±5V,
A
V
= +1, R
L
= 100Ω, Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
+SR
-SR (Note 5)
To 0.1%
To 0.05%
To 0.02%
VIDEO CHARACTERISTICS
Differential Gain
Differential Phase
f = 3.58MHz, A
V
= +2,
R
L
= 150Ω
f = 3.58MHz, A
V
= +2,
R
L
= 150Ω
B
B
25
25
-
-
0.02
0.03
-
-
%
Degrees
(NOTE 3)
TEST
LEVEL
B
B
B
B
B
TEMP.
(
o
C)
25
25
25
25
25
PARAMETER
Slew Rate
(V
OUT
= 5V
P-P
, A
V
= +2)
Settling Time
(V
OUT
= +2V to 0V step, Note 4)
MIN
-
-
-
-
-
TYP
1265
870
23
33
45
MAX
-
-
-
-
-
UNITS
V/μs
V/μs
ns
ns
ns
OUTPUT LIMITING CHARACTERISTICS
A
V
= +2, V
H
= +1V, V
L
= -1V, Unless Otherwise Specified
Limit Accuracy (Note 4)
Overdrive Recovery Time (Note 4)
Negative Limit Range
Positive Limit Range
Limit Input Bias Current
Limit Input Bandwidth
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Power Supply Current (Note 4)
C
A
A
NOTE:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See Typical Performance Curves for more information.
5. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive and
negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details.
25
25
Full
4.5
6.6
-
-
6.9
7.1
5.5
7.1
7.3
±V
mA
mA
V
IN
=
±1.6V,
A
V
= -1
V
IN
=
±1V
A
B
B
B
A
C
Full
25
25
25
Full
25
-
-
-125
-
-70
0.8
-5.0 to +2.5
-2.5 to +5.0
85
100
200
-
125
-
mV
ns
V
V
μA
MHz
Application Information
Relevant Application Notes
The following Application Notes pertain to the HFA1115:
• AN9653-Use and Application of Output Limiting
Amplifiers
• AN9752-Sync Stripper and Sync Inserter for
Composite Video
These publications may be obtained from Intersil’s web site
(http://www.intersil.com).
the two gain setting resistors, which frees up board space for
termination resistors.
Like most newer high performance amplifiers, the HFA1115
is a current feedback amplifier (CFA). CFAs offer high
bandwidth and slew rate at low supply currents, but can be
difficult to use because of their sensitivity to feedback
capacitance and parasitics on the inverting input (summing
node). The HFA1115 eliminates these concerns by bringing
the gain setting resistors on-chip. This yields the optimum
placement and value of the feedback resistor, while
minimizing feedback and summing node parasitics. Because
there is no access to the summing node, the PCB parasitics
do not impact performance at gains of +2 or -1 (see “Unity
Gain Considerations” for discussion of parasitic impact on
unity gain performance).
HFA1115 Advantages
The HFA1115 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
Implementing a gain of 2, cable driver with this IC eliminates
4
HFA1115
The HFA1115’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Another straightforward approach is to add a 620Ω resistor
in series with the positive input. This resistor and the
HFA1115 input capacitance form a low pass filter which rolls
off the signal bandwidth before gain peaking occurs. This
configuration was employed to obtain the datasheet AC and
transient parameters for a gain of +1.
Closed Loop Gain Selection
This “buffer” operates in closed loop gains of -1, +1, or +2, and
gain selection is accomplished via connections to the
±inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for layout caveats), while grounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded through a 50Ω resistor.
The table below summarizes these connections:
GAIN
(A
V
)
-1
+1
+2
CONNECTIONS
+INPUT (PIN 3)
50Ω to GND
Input
Input
-INPUT (PIN 2)
Input
NC (Floating)
GND
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be
≥50Ω.
This is especially
important in inverting gain configurations where the non-
inverting input would normally be connected directly to GND.
Pulse Undershoot and Asymmetrical Slew Rates
The HFA1115 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added
distortion for signals swinging below ground, and an
increased undershoot on the negative portion of the output
waveform (see Figures 9, 13, and 17). This undershoot isn’t
present for small bipolar signals, or large positive signals.
Another artifact of the composite device is asymmetrical slew
rates for output signals with a negative voltage component.
The slew rate degrades as the output signal crosses through
0V (see Figures 9, 13, and 17), resulting in a slower overall
negative slew rate. Positive only signals have symmetrical
slew rates as illustrated in the large signal positive pulse
response graphs (see Figures 7, 11, and 15).
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HFA1115. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance
associated with attaching the -Input lead to the PCB results
in approximately 3dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS
IMPLEMENTATIONS
PEAK-
ING
(dB)
2.5
0.6
0
0
0.2
±0.1dB
GAIN
FLATNESS
(MHz)
20
25
65
45
19
APPROACH
Remove Pin 2
+R
S
= 620Ω
+R
S
= 620Ω and
Remove Pin 2
Short Pins 2, 3
100pF cap. be-
tween pins 2, 3
BW
(MHz)
400
170
165
200
190
+SR/-SR
(V/μs)
1200/850
1125/800
1050/775
875/550
900/550
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board.
The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10μF) tantalum in parallel with a small value
(0.1μF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the input
and output of the device. Capacitance directly on the output
must be minimized, or isolated as discussed in the next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground at the amplifier’s
inverting input. At higher frequencies this capacitance tends
to short the -INPUT to GND, resulting in a closed loop gain
which increases with frequency. This causes excessive high
frequency peaking and potentially other problems as well.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 2.
Table 1 lists five alternate methods for configuring the
HFA1115 as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together, and
applying the input signal to this common node. The amplifier
bandwidth drops from 400MHz to 200MHz, but excellent
gain flatness is the benefit. Another drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
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stm32/stm8
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