EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

ISPLSI3320-70LM

Description
EE PLD, 18ns, 320-Cell, CMOS, PQFP208, MQFP-208
CategoryProgrammable logic devices    Programmable logic   
File Size218KB,16 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric Compare View All

ISPLSI3320-70LM Overview

EE PLD, 18ns, 320-Cell, CMOS, PQFP208, MQFP-208

ISPLSI3320-70LM Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLattice
Parts packaging codeQFP
package instructionMQFP-208
Contacts208
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresSYNCHRONOUS & ASYNCHRONOUS CLOCKS
maximum clock frequency50 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G208
JTAG BSTYES
length27.69 mm
Humidity sensitivity level1
Dedicated input times
Number of I/O lines160
Number of macro cells320
Number of terminals208
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 160 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)225
power supply5 V
Programmable logic typeEE PLD
propagation delay18 ns
Certification statusNot Qualified
Maximum seat height4.07 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width27.69 mm
Base Number Matches1

ISPLSI3320-70LM Related Products

ISPLSI3320-70LM ISPLSI3320-100LM
Description EE PLD, 18ns, 320-Cell, CMOS, PQFP208, MQFP-208 EE PLD, 13ns, 320-Cell, CMOS, PQFP208, MQFP-208
Is it Rohs certified? incompatible incompatible
Maker Lattice Lattice
Parts packaging code QFP QFP
package instruction MQFP-208 MQFP-208
Contacts 208 208
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Other features SYNCHRONOUS & ASYNCHRONOUS CLOCKS SYNCHRONOUS & ASYNCHRONOUS CLOCKS
maximum clock frequency 50 MHz 77 MHz
In-system programmable YES YES
JESD-30 code S-PQFP-G208 S-PQFP-G208
JTAG BST YES YES
length 27.69 mm 27.69 mm
Humidity sensitivity level 1 1
Number of I/O lines 160 160
Number of macro cells 320 320
Number of terminals 208 208
Maximum operating temperature 70 °C 70 °C
organize 0 DEDICATED INPUTS, 160 I/O 0 DEDICATED INPUTS, 160 I/O
Output function MACROCELL MACROCELL
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code FQFP FQFP
Encapsulate equivalent code QFP208,1.2SQ,20 QFP208,1.2SQ,20
Package shape SQUARE SQUARE
Package form FLATPACK, FINE PITCH FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius) 225 225
power supply 5 V 5 V
Programmable logic type EE PLD EE PLD
propagation delay 18 ns 13 ns
Certification status Not Qualified Not Qualified
Maximum seat height 4.07 mm 4.07 mm
Maximum supply voltage 5.25 V 5.25 V
Minimum supply voltage 4.75 V 4.75 V
Nominal supply voltage 5 V 5 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 27.69 mm 27.69 mm

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号