Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9328MX21
Rev. 3.1, 07/2006
MC9328MX21
Package Information
MC9328MX21
266 MHz
(MAPBGA–289)
Ordering Information: See Table 1 on page 3
1
Introduction
Contents
1
2
3
4
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal Descriptions . . . . . . . . . . . . . . . . . . . . 5
Specifications . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Assignment and Package Information 95
Document Revision History . . . . . . . . . . . . 98
Freescale’s i.MX family of microprocessors has
demonstrated leadership in the portable handheld
market. Building on the success of the MX (Media
Extensions) series, the i.MX21 (MC9328MX21)
provides a leap in performance with an ARM926EJ-S
™
microprocessor core that provides accelerated Java
support in addition to highly integrated system functions.
The i.MX21 device specifically addresses the needs of
the smartphone and portable product markets with
intelligent integrated peripherals, advanced processor
core, and power management capabilities.
Thei.MX21 features the advanced and power-efficient
ARM926EJ-S core operating at speeds up to 266 MHz
and is part of a growing family of
Smart Speed
products
that offer high performance processing optimized for
lowest power consumption. On-chip modules such as a
video accelerator module, LCD controller, USB On-The-
Go, 1-Wire
®
interface, CMOS sensor interface, and
synchronous serial interfaces offer designers a rich suite
of peripherals that can enhance many products seeking to
provide a rich multimedia experience.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the
design of its products.
© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Introduction
For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash
devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC)
and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN,
Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers.
The device is packaged in a 289-pin MAPBGA.
System Control
JTAG/Multi
ICE
System Boot
Clock Management
Connectivity
i.MX21
CSPI x 3
SSI x 2
I
2
C
ARM9 Platform
Standard System I/O
Timers x 3
PWM
WDOG
RTC
GPIO
DMAC
D Cache
Internal Control
Bus Control
Memory Control
ARM926EJ-S
I Cache
MAX
MMU
Audio Mux
UART x 4
1-WIRE
IrDA
USB OTG/ 2 Hosts
Memory Expansion
MMC/SD x 2
PCMCIA/CF
Human Interface
CSI
LCD Controller
SLCD Controller
Keypad
Enhanced Multimedia Accelerator
(eMMA)
Pre- and Post- Processing
Memory Interface
SDRAMC
EIM/BMI
Video Accelerator
NFC
Figure 1. i.MX21 Functional Block Diagram
1.1
•
•
•
•
•
•
Conventions
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one
is a voltage that corresponds to Boolean true (1) state.
Logic level zero
is a voltage that corresponds to Boolean false (0) state.
To
set
a bit or bits means to establish logic level one.
To
clear
a bit or bits means to establish logic level zero.
A
signal
is an electronic construct whose state conveys or changes in state convey information.
This document uses the following conventions:
MC9328MX21 Technical Data, Rev. 3.1
2
Freescale Semiconductor
Introduction
•
•
•
•
•
A
pin
is an external physical connection. The same pin can be used to connect a number of signals.
Asserted
means that a discrete signal is in active logic state.
—
Active low
signals change from logic level one to logic level zero.
—
Active high
signals change from logic level zero to logic level one.
Negated
means that an asserted discrete signal changes logic state.
—
Active low
signals change from logic level zero to logic level one.
—
Active high
signals change from logic level one to logic level zero.
LSB means
least significant bit
or
bits,
and MSB means
most significant bit
or
bits.
References to low and
high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or
0x
are
hexadecimal.
1.2
Target Applications
The i.MX21 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3
audio players, handheld computers based on the popular Palm OS platform, and messaging applications.
1.3
Reference Documentation
The following documents are required for a complete description of the i.MX21 and are necessary to
design properly with the device. Especially for those not familiar with the ARM926EJ-S processor the
following documents are helpful when used in conjunction with this manual.
ARM Architecture Reference Manual
(ARM Ltd., order number ARM DDI 0100)
ARM7TDMI Data Sheet
(ARM Ltd., order number ARM DDI 0029)
ARM920T Technical Reference Manual
(ARM Ltd., order number ARM DDI 0151C)
MC9328MX21 Product Brief
(order number MC9328MX21P)
MC9328MX21 Reference Manual
(order number MC9328MX21RM)
The Freescale manuals are available on the Freescale Semiconductor Web site at http://
www.freescale.com. These documents may be downloaded directly from the Freescale Web site, or printed
versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
1.4
Ordering Information
Table 1. Ordering Information
Part Order Number
Package Size
289-lead MAPBGA
0.65mm, 14mm x 14mm
289-lead MAPBGA
0.8mm, 17mm x 17mm
289-lead MAPBGA
0.65mm, 14mm x 14mm
289-lead MAPBGA
0.8mm, 17mm x 17mm
Package Type
Lead-free
Lead-free
Lead-free
Lead-free
Operating Range
0
°
C–70
°
C
0
°
C–70
°
C
-30
°
C–70
°
C
-30
°
C–70
°
C
Table 1
provides ordering information for the device.
MC9328MX21VK
MC9328MX21VM
MC9328MX21DVK
MC9328MX21DVM
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
3
Introduction
Table 1. Ordering Information (Continued)
Part Order Number
MC9328MX21CVK
MC9328MX21CVM
Package Size
289-lead MAPBGA
0.65mm, 14mm x 14mm
289-lead MAPBGA
0.8mm, 17mm x 17mm
Package Type
Lead-free
Lead-free
Operating Range
-40
°
C–85
°
C
-40
°
C–85
°
C
1.5
Features
The i.MX21 boasts a robust array of features that can support a wide variety of applications. Below is a
brief description of i.MX21 features.
•
•
•
ARM926EJ-S Core Complex
enhanced Multimedia Accelerator (eMMA)
Display and Video Modules
— LCD Controller (LCDC)
— Smart LCD Controller (SLCDC)
— CMOS Sensor Interface (CSI)
Bus Master Interface (BMI)
Wireless Connectivity
— Fast Infra-Red Interface (FIRI)
Wired Connectivity
— USB On-The-Go (USBOTG) Controller
— Four Universal Asynchronous Receiver/Transmitters (UARTx)
— Three Configurable Serial Peripheral Interfaces (CSPIx) for High Speed Data Transfer
— Inter-IC (I
2
C) Bus Module
— Two Synchronous Serial Interfaces (SSI) with Inter-IC Sound (I
2
S)
— Digital Audio Mux
— One-Wire Controller
— Keypad Interface
Memory Expansion and I/O Card Support
— Two Multimedia Card and Secure Digital (MMC/SD) Host Controller Modules
Memory Interface
— External Interface Module (EIM)
— SDRAM Controller (SDRAMC)
— NAND Flash Controller (NFC)
— PCMCIA/CF Interface
Standard System Resources
— Clock Generation Module (CGM) and Power Control Module
— Three General-Purpose 32-Bit Counters/Timers
— Watchdog Timer
— Real-Time Clock/Sampling Timer (RTC)
— Pulse-Width Modulator (PWM) Module
— Direct Memory Access Controller (DMAC)
— General-Purpose I/O (GPIO) Ports
— Debug Capability
MC9328MX21 Technical Data, Rev. 3.1
4
Freescale Semiconductor
•
•
•
•
•
•
Signal Descriptions
2
Signal Descriptions
Table 2
identifies and describes the i.MX21 signals. Pin assignment is provided in
Section 4, “Pin
Assignment and Package Information”
and in the “Signal Multiplexing Scheme” table within the reference
manual.
The connections of the pins in
Table 2
depends solely upon the user application, however there are a few
factory test signals that are not used in a normal application. Following is a list of these signals and how
they are to be terminated for proper operation of the i.MX21 processor:
• CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
• OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
• EXT_48M: To ensure proper operation, connect this signal to ground.
• EXT_266M: To ensure proper operation, connect this signal to ground.
• TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate
keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed
function, then configure as GPIO input with pull up enabled, and leave as a no connect.
• TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
Table 2. i.MX21 Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [25:0]
D [31:0]
EB0
EB1
EB2
EB3
OE
CS [5:0]
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM
DQM0.
Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2
and PCMCIA PC_REG.
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is
selected. DTACK is multiplexed with CS4.
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-
going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also
shared with the PCMCIA PC_WE.
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
ECB
LBA
BCLK
RW
DTACK
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
5
Microcontroller MCU
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