74ABT162244 16-Bit Buffer/Line Driver with 25: Series Resistors in the Outputs
April 1992
Revised May 2005
74ABT162244
16-Bit Buffer/Line Driver with
25: Series Resistors in the Outputs
General Description
The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmit-
ter/receiver. The device is nibble controlled. Individual
3-STATE control inputs can be shorted together for 8-bit or
16-bit operation.
The 25
:
series resistors in the outputs reduce ringing and
eliminate the need for external resistors.
Features
s
Separate control logic for each nibble
s
16-bit version of the ABT2244
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
Ordering Code:
Order Number
74ABT162244CSSC
74ABT162244CSSX
74ABT162244CMTD
74ABT162244MTDX
Package Number
MS48A
MS48A
MTD48
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation
DS010987
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74ABT162244
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
3
L
L
H
Inputs
OE
2
L
L
H
Inputs
OE
4
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Logic Diagram
Outputs
I
0
–I
3
L
H
X
O
0
–O
3
L
H
Z
Outputs
I
8
–I
11
L
H
X
O
8
–O
11
L
H
Z
Outputs
I
4
–I
7
L
H
X
O
4
–O
7
L
H
Z
Outputs
I
12
–I
15
L
H
X
O
12
–O
15
L
H
Z
Schematic of each Output
Functional Description
The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.
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2
74ABT162244
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
125
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to 5.5V
0.5V to V
CC
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
500 mA
10V
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
4.75
2.5
2.0
0.8
1
1
7
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
V
V
Min
Min
Min
Min
Max
Max
Max
0.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
V
IN
V
IN
V
IN
V
IN
V
IN
I
ID
1.2
18 mA
3 mA
32 mA
12 mA
2.7V (Note 3)
V
CC
7.0V
0.5V (Note 3)
0.0V
1.9
P
A
P
A
P
A
P
A
V
1
1
All Other Pins Grounded
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output High Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
(Note 3)
Note 3:
Guaranteed, but not tested.
10
P
A
P
A
mA
0
5.5V V
OUT
0
5.5V V
OUT
Max
Max
0.0
Max
Max
Max
V
OUT
V
OUT
V
OUT
2.7V; OE
n
0.5V; OE
n
0.0V
V
CC
2.0V
2.0V
10
100
275
50
100
2.0
60
2.0
3.0
3.0
50
P
A
P
A
mA
mA
mA
mA
mA
5.5V; All Others GND
All Outputs HIGH
All Outputs LOW
OE
n
V
I
V
CC
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
All Others at V
CC
or GND
Max
Enable Input V
I
Data Input V
I
Outputs OPEN
OE
n
GND
One Bit Toggling, 50% Duty Cycle
P
A
mA/
All Others at V
CC
or GND
No Load
0.1
MHz
Max
3
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74ABT162244
AC Electrical Characteristics
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation
Delay Data to Outputs
Output
Enable Time
Output
Disable Time
1.0
1.0
1.5
1.5
1.0
1.0
V
CC
C
L
25
q
C
5V
50 pF
Typ
2.4
3.2
3.5
4.2
4.2
3.8
Max
3.9
4.7
6.3
6.9
6.7
6.7
T
A
40
q
C to
85
q
C
4.5V–5.5V
50 pF
Max
3.9
4.7
6.3
6.9
6.7
6.7
ns
ns
ns
Units
C
L
V
CC
Min
1.0
1.0
1.5
1.5
1.0
1.0
Capacitance
Symbol
C
IN
C
OUT
(Note 4)
Parameter
Input Capacitance
Output Capacitance
Typ
5.0
9.0
1 MHz per MIL-STD-883, Method 3012.
Units
pF
pF
V
CC
V
CC
0.0V
5.0V
Conditions
T
A
25
q
C
Note 4:
C
OUT
is measured at frequency f
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74ABT162244
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Input Pulse Requirements
Amplitude
3.0V
Rep. Rate
1 MHz
t
W
500 ns
t
r
2.5 ns
t
f
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting
and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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