CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Parameter Name | Attribute value |
Is it Rohs certified? | conform to |
Maker | Lattice |
Parts packaging code | BGA |
package instruction | FPBGA-256 |
Contacts | 256 |
Reach Compliance Code | not_compliant |
ECCN code | EAR99 |
Is Samacsys | N |
Other features | YES |
maximum clock frequency | 86 MHz |
In-system programmable | YES |
JESD-30 code | S-PBGA-B256 |
JESD-609 code | e1 |
JTAG BST | YES |
length | 17 mm |
Humidity sensitivity level | 3 |
Dedicated input times | 4 |
Number of I/O lines | 192 |
Number of macro cells | 384 |
Number of terminals | 256 |
organize | 4 DEDICATED INPUTS, 192 I/O |
Output function | MACROCELL |
Package body material | PLASTIC/EPOXY |
encapsulated code | BGA |
Encapsulate equivalent code | BGA256,16X16,40 |
Package shape | SQUARE |
Package form | GRID ARRAY |
Peak Reflow Temperature (Celsius) | 250 |
power supply | 1.8 V |
Programmable logic type | EE PLD |
propagation delay | 10 ns |
Certification status | Not Qualified |
Maximum seat height | 2.1 mm |
Maximum supply voltage | 1.95 V |
Minimum supply voltage | 1.65 V |
Nominal supply voltage | 1.8 V |
surface mount | YES |
technology | CMOS |
Terminal surface | Tin/Silver/Copper (Sn/Ag/Cu) |
Terminal form | BALL |
Terminal pitch | 1 mm |
Terminal location | BOTTOM |
Maximum time at peak reflow temperature | 40 |
width | 17 mm |
Base Number Matches | 1 |