AX250-2FG256 datasheet, PDF - EEWORLD Datasheet

AX250-2FG256: DescriptionFPGA - Field Programmable Gate Array Axcelerator (AX); CategoryProgrammable logic devices Programmable logic; File Size13MB，262 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

AX250-2FG256 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	AX250-2FG256	-	-	View	Buy Now

FPGA - Field Programmable Gate Array Axcelerator (AX)

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	LBGA, BGA256,16X16,40
Reach Compliance Code	compliant
Other features	250000 SYSTEM GATES AVAILABLE
maximum clock frequency	870 MHz
Combined latency of CLB-Max	0.74 ns
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	2816
Equivalent number of gates	250000
Number of entries	248
Number of logical units	4224
Output times	248
Number of terminals	256
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2816 CLBS, 250000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	225
power supply	1.5,1.5/3.3,2.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD/TIN LEAD SILVER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	17 mm
Base Number Matches	1

Transistor Circuit Design (Volumes 1 and 2): This book is one of the "Practical Electronic Circuit Design Series" and is divided into two volumes.The main contents of the first volume include the working principle of transistors, the performance...; arui1999 Download Centre

Design of multi-machine communication dispatching and commanding system based on I2C bus: This paper introduces the structure, working principle, and data transmission mode of the I2C bus, discusses the design of multi-machine communication software and hardware based on the I2C bus, and r...; Jacktang RF/Wirelessly

[Xianji HPM6750 Review 4] SPI peripheral verification of two screen refresh performances: [i=s]This post was last edited by RCSN on 2022-5-8 19:05[/i]This post is for the SPI display driver interface of the subsequent lvgl porting. Since there is no RGB screen, only the SPI interface displ...; RCSN Domestic Chip Exchange

Qorvo Solution Interoperates with Apple* U1 Chip, Enabling New Ultra-Wideband Experiences: Qorvo (Nasdaq: QRVO), a leading provider of innovative RF solutions for mobile, infrastructure and aerospacedefense applications, today announced that its DW3000 family of products interoperates with ...; 兰博 RF/Wirelessly

Make a beautiful snowflake crystal ball: From: https://learn.adafruit.com/snow-globe-b ... b?view=allHave fun creating your own snow globe any time of year! Using a Circuit Playground Bluefruit running CircuitPython, detect shakes with the b...; dcexpert MicroPython Open Source section

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components