SI5321-G-BC datasheet, PDF - EEWORLD Datasheet

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SI5321-G-BC: DescriptionClock Generators & Support Products SONET/SDH Precision Clock 19 to 2500MHz; Categorysemiconductor Analog mixed-signal IC; File Size395KB，34 Pages; ManufacturerSilicon Laboratories

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SI5321-G-BC Overview

Clock Generators & Support Products SONET/SDH Precision Clock 19 to 2500MHz

SI5321-G-BC Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Clock Generators & Support Products
RoHS	Details
Type	Clock Multipliers
Operating Supply Voltage	3.3 V
Minimum Operating Temperature	- 20 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	CBGA-63
Packaging	Tray
Moisture Sensitive	Yes
Factory Pack Quantity	260
Unit Weight	0.017772 oz

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Si5321

SONET/SDH P

R E C I S IO N

LOCK

ULTIPLIER

I C

Features

Ultra-low jitter clock output with jitter

generation as low as 0.3 ps

RMS

No external components (other than a

resistor and bypassing)

Input clock ranges at 19, 39, 78, 155,

311, or 622 MHz

Output clock ranges at 19, 39, 78, 155,

311, 622, 1244, or 2488 MHz

Maximum range includes 693 MHz for

10 GbE FEC support

Digital hold for loss-of-input clock

Support for 255/238 (15/14),

255/237 (85/79), and 66/64 FEC scaling

(ITU-T G.709 and IEEE 802.3ae)

Selectable loop bandwidth

Loss-of-signal alarm output

Low power

Small size (9 x 9 mm)

Backwards compatible with Si5320

Si5321

Applications

SONET/SDH line/port cards

Terabit routers

Core switches

Digital cross connects

Ordering Information:

See page 30.

Description

The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed

communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device

phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range

and generates a frequency-multiplied clock output that can be configured for operation

in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories

DSPLL

technology provides PLL functionality with unparalleled performance. It

eliminates external loop filter components, provides programmable loop parameters,

and simplifies design. FEC rates are supported by selectable forward and reverse 255/

238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. The ITU-T G.709

255/237 rate and the IEEE 802.3ae 66/64 rate are supported when using a 155 MHz or

higher rate input clock. The performance and integration of Silicon Laboratories’ Si5321

clock IC provides high-level support of the latest specifications and systems. It operates

from a single 3.3 V supply.

Functional Block Diagram

REXT

VSEL33

VDD

GND

Biasing & Supply Regulation

FXDDELAY

CLKIN+

CLKIN–

CAL_ACTV

Signal

Detect

DSPLL

DH_ACTV

Calibration

CLKOUT+

CLKOUT–

FRQSEL[2:0]

RSTN/CAL

VALTIME

LOS

BWBOOST

BWSEL[1:0]

INFRQSEL[2:0] FEC[2:0]

Rev. 2.5 8/08

Si5321

Si5321

ABLE

ECTION

ONTENTS

AGE

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1. DSPLL

® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.5. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3. Pin Descriptions: Si5321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6. 9x9 mm PBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Rev. 2.5

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