C8051F020/1/2/3
8K ISP FLASH MCU Family
ANALOG PERIPHERALS
-
SAR ADC
•
12-Bit (C8051F020/1)
•
10-Bit (C8051F022/3)
•
± 1 LSB INL
•
Programmable Throughput up to 100 ksps
•
Up to 8 External Inputs; Programmable as Single-Ended or
•
•
•
-
•
•
•
-
•
Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data-Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (± 3°C)
Programmable Throughput up to 500 ksps
8 External Inputs
Programmable Amplifier Gain: 4, 2, 1, 0.5
Can Synchronize Outputs to Timers for Jitter-Free Wave-
form Generation
HIGH SPEED 8051
μC
CORE
-
Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
-
Up to 25 MIPS Throughput with 25 MHz Clock
-
22 Vectored Interrupt Sources
MEMORY
-
4352 Bytes Internal Data RAM (4k + 256)
-
64k Bytes FLASH; In-System programmable in 512-byte
-
Sectors
External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)
8-bit ADC
DIGITAL PERIPHERALS
-
8 Byte-Wide Port I/O (C8051F020/2); 5V tolerant
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4 Byte-Wide Port I/O (C8051F021/3); 5V tolerant
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Hardware SMBus™ (I
2
C™ Compatible), SPI™, and
-
Two UART Serial Ports Available Concurrently
Programmable 16-bit Counter/Timer Array with
5 Capture/Compare Modules
5 General Purpose 16-bit Counter/Timers
Dedicated Watch-Dog Timer; Bi-directional Reset Pin
Two 12-bit DACs
-
Two Analog Comparators
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Voltage Reference
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Precision VDD Monitor/Brown-Out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
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On-Chip Debug Circuitry Facilitates Full- Speed, Non-
-
-
-
-
Intrusive In-Circuit/In-System Debugging
Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers
Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
IEEE1149.1 Compliant Boundary Scan
Low-Cost,
Complete
Development Kit
-
-
CLOCK SOURCES
-
Internal Programmable Oscillator: 2-to-16 MHz
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External Oscillator: Crystal, RC, C, or Clock
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Real-Time Clock Mode using Timer 3 or PCA
SUPPLY VOLTAGE .......................... 2.7V TO 3.6V
-
Typical Operating Current: 10 mA @ 20 MHz
-
Multiple Power Saving Sleep and Shutdown Modes
100-Pin TQFP and 64-Pin TQFP Packages Available
Temperature Range: -40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
DIGITAL I/O
UART0
Port 0
CROSSBAR
External Memory Interface
AMUX
PGA
VREF
10/12-bit
100ksps
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
ADC
8-bit
500ksps
ADC
+
-
AMUX
+
-
PGA
12-Bit
DAC
12-Bit
DAC
VOLTAGE
COMPARATORS
64 pin
100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
22
INTERRUPTS
64KB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
JTAG
SRAM
CLOCK
SANITY
CIRCUIT
CONTROL
Rev. 1.4 12/03
Copyright © 2003 by Silicon Laboratories
C8051F020/1/2/3
C8051F020/1/2/3
Notes
2
Rev. 1.4
C8051F020/1/2/3
TABLE OF CONTENTS
1. SYSTEM OVERVIEW .........................................................................................................17
1.1. CIP-51™ Microcontroller Core ......................................................................................22
1.1.1. Fully 8051 Compatible ..........................................................................................22
1.1.2. Improved Throughput ............................................................................................22
1.1.3. Additional Features................................................................................................23
1.2. On-Chip Memory ............................................................................................................24
1.3. JTAG Debug and Boundary Scan ...................................................................................25
1.4. Programmable Digital I/O and Crossbar .........................................................................26
1.5. Programmable Counter Array .........................................................................................27
1.6. Serial Ports.......................................................................................................................27
1.7. 12-Bit Analog to Digital Converter.................................................................................28
1.8. 8-Bit Analog to Digital Converter...................................................................................29
1.9. Comparators and DACs...................................................................................................30
2. ABSOLUTE MAXIMUM RATINGS ..................................................................................31
3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................32
4. PINOUT AND PACKAGE DEFINITIONS........................................................................33
5. ADC0 (12-BIT ADC, C8051F020/1 ONLY) ........................................................................43
5.1. Analog Multiplexer and PGA..........................................................................................43
5.2. ADC Modes of Operation ...............................................................................................44
5.2.1. Starting a Conversion.............................................................................................44
5.2.2. Tracking Modes .....................................................................................................45
5.2.3. Settling Time Requirements ..................................................................................46
5.3. ADC0 Programmable Window Detector.........................................................................53
6. ADC0 (10-BIT ADC, C8051F022/3 ONLY) ........................................................................59
6.1. Analog Multiplexer and PGA..........................................................................................59
6.2. ADC Modes of Operation ...............................................................................................60
6.2.1. Starting a Conversion.............................................................................................60
6.2.2. Tracking Modes .....................................................................................................61
6.2.3. Settling Time Requirements ..................................................................................62
6.3. ADC0 Programmable Window Detector.........................................................................69
7. ADC1 (8-BIT ADC) ...............................................................................................................75
7.1. Analog Multiplexer and PGA..........................................................................................75
7.2. ADC1 Modes of Operation .............................................................................................76
7.2.1. Starting a Conversion.............................................................................................76
7.2.2. Tracking Modes .....................................................................................................76
7.2.3. Settling Time Requirements ..................................................................................78
8. DACS, 12-BIT VOLTAGE MODE ......................................................................................83
8.1. DAC Output Scheduling..................................................................................................83
8.1.1. Update Output On-Demand ...................................................................................84
8.1.2. Update Output Based on Timer Overflow .............................................................84
8.2. DAC Output Scaling/Justification...................................................................................84
9. VOLTAGE REFERENCE (C8051F020/2)..........................................................................91
Rev. 1.4
3
C8051F020/1/2/3
10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93
11. COMPARATORS..................................................................................................................95
12. CIP-51 MICROCONTROLLER........................................................................................101
12.1. Instruction Set................................................................................................................102
12.1.1. Instruction and CPU Timing................................................................................102
12.1.2. MOVX Instruction and Program Memory...........................................................102
12.2. Memory Organization ...................................................................................................107
12.2.1. Program Memory .................................................................................................107
12.2.2. Data Memory .......................................................................................................108
12.2.3. General Purpose Registers ...................................................................................108
12.2.4. Bit Addressable Locations ...................................................................................108
12.2.5. Stack .................................................................................................................108
12.2.6. Special Function Registers...................................................................................109
12.2.7. Register Descriptions ...........................................................................................113
12.3. Interrupt Handler ...........................................................................................................116
12.3.1. MCU Interrupt Sources and Vectors ...................................................................116
12.3.2. External Interrupts ...............................................................................................116
12.3.3. Interrupt Priorities................................................................................................118
12.3.4. Interrupt Latency..................................................................................................118
12.3.5. Interrupt Register Descriptions ............................................................................119
12.4. Power Management Modes ...........................................................................................125
12.4.1. Idle Mode .............................................................................................................125
12.4.2. Stop Mode............................................................................................................125
13. RESET SOURCES ..............................................................................................................127
13.1. Power-on Reset..............................................................................................................128
13.2. Power-fail Reset ............................................................................................................128
13.3. External Reset................................................................................................................129
13.4. Software Forced Reset...................................................................................................129
13.5. Missing Clock Detector Reset .......................................................................................129
13.6.Comparator0 Reset ........................................................................................................129
13.7. External CNVSTR Pin Reset.........................................................................................129
13.8. Watchdog Timer Reset ..................................................................................................129
13.8.1. Enable/Reset WDT ..............................................................................................130
13.8.2. Disable WDT .......................................................................................................130
13.8.3. Disable WDT Lockout.........................................................................................130
13.8.4. Setting WDT Interval...........................................................................................130
14. OSCILLATORS...................................................................................................................135
14.1. External Crystal Example..............................................................................................138
14.2. External RC Example ....................................................................................................138
14.3. External Capacitor Example..........................................................................................138
15. FLASH MEMORY ..............................................................................................................139
15.1. Programming The FLASH Memory .............................................................................139
15.2. Non-volatile Data Storage .............................................................................................140
15.3. Security Options ............................................................................................................140
16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145
4
Rev. 1.4
C8051F020/1/2/3
16.1. Accessing XRAM..........................................................................................................145
16.1.1. 16-Bit MOVX Example.......................................................................................145
16.1.2. 8-Bit MOVX Example.........................................................................................145
16.2. Configuring the External Memory Interface .................................................................146
16.3. Port Selection and Configuration ..................................................................................146
16.4. Multiplexed and Non-multiplexed Selection.................................................................148
16.4.1. Multiplexed Configuration ..................................................................................148
16.4.2. Non-multiplexed Configuration...........................................................................149
16.5. Memory Mode Selection ...............................................................................................150
16.5.1. Internal XRAM Only ...........................................................................................150
16.5.2. Split Mode without Bank Select ..........................................................................150
16.5.3. Split Mode with Bank Select ...............................................................................151
16.5.4. External Only .......................................................................................................151
16.6. Timing .......................................................................................................................151
16.6.1. Non-multiplexed Mode........................................................................................153
16.6.1.1. 16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’................................153
16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’............154
16.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ..............................155
16.6.2. Multiplexed Mode................................................................................................156
16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’................................156
16.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’............157
16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ..............................158
17. PORT INPUT/OUTPUT .....................................................................................................161
17.1. Ports 0 through 3 and the Priority Crossbar Decoder....................................................163
17.1.1. Crossbar Pin Assignment and Allocation ............................................................163
17.1.2. Configuring the Output Modes of the Port Pins ..................................................164
17.1.3. Configuring Port Pins as Digital Inputs ...............................................................165
17.1.4. External Interrupts (IE6 and IE7) ........................................................................165
17.1.5. Weak Pull-ups......................................................................................................165
17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])......................................165
17.1.7. External Memory Interface Pin Assignments ......................................................166
17.1.8. Crossbar Pin Assignment Example......................................................................168
17.2.Ports 4 through 7 (C8051F020/2 only)..........................................................................177
17.2.1. Configuring Ports which are not Pinned Out.......................................................177
17.2.2. Configuring the Output Modes of the Port Pins ..................................................177
17.2.3. Configuring Port Pins as Digital Inputs ...............................................................178
17.2.4. Weak Pull-ups......................................................................................................178
17.2.5. External Memory Interface ..................................................................................178
18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183
18.1.Supporting Documents ..................................................................................................184
18.2.SMBus Protocol.............................................................................................................185
18.2.1. Arbitration............................................................................................................185
18.2.2. Clock Low Extension...........................................................................................185
18.2.3. SCL Low Timeout ...............................................................................................186
18.2.4. SCL High (SMBus Free) Timeout.......................................................................186
Rev. 1.4
5
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