PI6C20400ALE datasheet, PDF - EEWORLD Datasheet

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PI6C20400ALE: DescriptionClock Buffer 1:4 PCI Express Gen 2 Zero Delay Buffer; Categorylogic logic; File Size639KB，11 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/; Environmental Compliance

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PI6C20400ALE Overview

Clock Buffer 1:4 PCI Express Gen 2 Zero Delay Buffer

PI6C20400ALE Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP28,.25
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
series	TTL
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	R-PDSO-G28
JESD-609 code	e3
length	9.7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.001 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	28
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP28,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	6.5 ns
propagation delay (tpd)	0.25 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	4.4 mm

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PI6C20400A

1:4 Clock Driver for Intel PCIe® Chipsets

Features

• Phase jitter filter for PCIe® 2.0 application

• Four Pairs of Differential Clocks

• Low skew < 50ps

• Low jitter < 50ps cycle-to-cycle

• < 1 ps additive RMS phase jitter

• Output Enable for all outputs

• Outputs tristate control via SMBus

• Programmable PLL Bandwidth

• 100 MHz PLL Mode operation

• 100 - 400 MHz Bypass Mode operation

• 3.3V Operation

• Packaging (Pb-free and Green):

→28-Pin SSOP (H28)

→28-Pin TSSOP (L28)

Description

Pericom Semiconductor's PI6C20400A is a PCIe® 2.0 compliant

high-speed, low-noise differential clock buffer designed to be

companion to PI6C410BS. The device distributes the differential

SRC clock from PI6C410BS to four differential pairs of clock

outputs either with or without PLL. The clock outputs are

controlled by input selection of SRC_STOP#, PWRDWN# and

SMBus, SCLK and SDA. When input of either SRC_STOP#

or PWRDWN# is low, the output clocks are Tristated. When

PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated.

Block Diagram

OE_INV

OE_0 & OE_3

SRC_STOP#

PWRDWN#

Pin Configuration

SRC

SRC#

OUT0

OUT0#

OE_0

OUT1

OUT1#

PLL/BYPASS#

SCLK

SDA

Output

Control

OUT0

OUT0#

SMBus

Controller

OUT1

OUT1#

OUT2

OUT2#

OUT3

OUT3#

SCLK

SDA

PLL/BYPASS#

SRC

SRC#

PLL_BW#

DIV

PLL

DD_A

SS_A

REF

OE_INV

OUT3

OUT3#

OE_3

OUT2

OUT2#

PLL_BW#

SRC_STOP#

PWRDWN#

14-0195

www.pericom.com

03/27/13

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