NTMD2C02R2
Preferred Device
Power MOSFET
2 Amps, 20 Volts
Complementary SOIC−8, Dual
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc−dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives.
Features
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2 AMPERES
20 VOLTS
R
DS(on)
= 43 mW (N−Channel)
R
DS(on)
= 120 mW (P−Channel)
N−Channel
D
P−Channel
D
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends
•
•
•
•
•
•
•
Battery Life
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
Miniature SOIC−8 Surface Mount Package
−
Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
I
DSS
Specified at Elevated Temperature
Mounting Information for SOIC−8 Package Provided
Pb−Free Packages are Available
G
S
G
S
8
1
SOIC−8
CASE 751
STYLE 14
MARKING DIAGRAM &
PIN ASSIGNMENT
ND ND PD PD
8
D2C02x
AYWW
G
G
1
NS NG PS PG
D2C02
x
A
Y
WW
G
= Specific Device Code
= Blank or S
= Assembly Location
= Year
= Work Week
= Pb−Free Package
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted) (Note 1)
Rating
Drain−to−Source Voltage
N−Channel
P−Channel
Gate−to−Source Voltage
Drain Current
−
Continuous
−
Pulsed
N−Channel
P−Channel
N−Channel
P−Channel
Symbol
V
DSS
Value
20
20
±12
5.2
3.4
48
17
−55
to
150
2.0
62.5
260
Unit
Vdc
V
GS
I
D
I
DM
T
J
and
T
stg
P
D
R
qJA
T
L
Vdc
A
(Note: Microdot may be in either location)
°C
W
°C/W
°C
NTMD2C02R2SG
Operating and Storage Temperature Range
Total Power Dissipation @ T
A
= 25°C
(Note 2)
Thermal Resistance
−
Junction to Ambient
(Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds.
ORDERING INFORMATION
Device
NTMD2C02R2
NTMD2C02R2G
Package
SOIC−8
Shipping
†
2500/Tape & Reel
SOIC−8 2500/Tape & Reel
(Pb−Free)
SOIC−8 2500/Tape & Reel
(Pb−Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Negative signs for P−Channel device omitted for clarity.
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with
one die operating, 10 sec. max.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
March, 2006
−
Rev. 1
1
Publication Order Number:
NTMD2C02R2/D
NTMD2C02R2
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted) (Note 3)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Zero Gate Voltage Drain Current
(V
GS
= 0 Vdc, V
DS
= 20 Vdc)
(V
GS
= 0 Vdc, V
DS
= 12 Vdc)
Gate−Body Leakage Current
(V
GS
=
±
12 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 4)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Drain−to−Source On−Resistance
(V
GS
= 4.5 Vdc, I
D
= 4.0 Adc)
(V
GS
= 4.5 Vdc, I
D
= 2.4 Adc)
Drain−to−Source On−Resistance
(V
GS
= 2.7 Vdc, I
D
= 2.0 Adc)
(V
GS
= 2.7 Vdc, I
D
= 1.2 Adc)
Forward Transconductance
(V
DS
= 2.5 Vdc, I
D
= 2.0 Adc)
(V
DS
= 2.5 Vdc, I
D
= 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
(V
DS
= 10 Vdc, I
D
= 4.0 Adc,
V
GS
= 4.5 Vdc)
(V
DS
= 6.0 Vdc, I
D
= 2.0 Adc,
V
GS
= 4.5 Vdc)
(V
DS
= 16 Vdc, I
D
= 6.0 Adc,
V
GS
= 4.5 Vdc,
R
G
= 6.0
W)
(V
DS
= 10 Vdc, I
D
= 2.4 Adc,
V
GS
= 4.5 Vdc,
R
G
= 6.0
W)
(V
DD
= 16 Vdc, I
D
= 4.0 Adc,
V
GS
= 4.5 Vdc,
R
G
= 6.0
W)
(V
DD
= 10 Vdc, I
D
= 1.2 Adc,
V
GS
= 2.7 Vdc,
R
G
= 6.0
W)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
11
15
35
40
45
35
60
35
12
10
50
35
45
33
80
29
12
10
1.5
1.5
4.0
5.0
3.0
3.0
18
−
65
−
75
−
110
−
20
20
90
65
75
60
130
55
20
18
−
−
−
−
−
−
nC
ns
(V
DS
= 10 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
(N)
(P)
(N)
(P)
(N)
(P)
−
−
−
−
−
−
785
540
210
215
75
100
1100
750
450
325
180
175
pF
V
GS(th)
R
DS(on)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
0.6
0.6
−
0.07
−
0.1
3.0
3.0
0.9
0.9
0.028
−
0.033
−
6.0
4.75
1.2
1.2
0.043
0.1
0.048
0.13
−
−
Vdc
W
V
(BR)DSS
I
DSS
(N)
(P)
(N)
(P)
−
20
20
−
−
−
−
−
−
−
−
−
−
1.0
1.0
100
Vdc
mAdc
Symbol
Polarity
Min
Typ
Max
Unit
I
GSS
nAdc
R
DS(on)
W
g
FS
Mhos
3. Negative signs for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
5. Switching characteristics are independent of operating junction temperature.
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2
NTMD2C02R2
ELECTRICAL CHARACTERISTICS
−
continued
(T
A
= 25°C unless otherwise noted) (Note 6)
Characteristic
SOURCE−DRAIN DIODE CHARACTERISTICS
(T
C
= 25°C)
Forward Voltage (Note 7)
Reverse Recovery Time
(I
S
= 4.0 Adc, V
GS
= 0 Vdc)
(I
S
= 2.4 Adc, V
GS
= 0 Vdc)
V
SD
t
rr
t
a
(I
F
= I
S
,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
6. Negative signs for P−Channel device omitted for clarity.
7. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
t
b
Q
RR
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
(N)
(P)
−
−
−
−
−
−
−
−
−
−
0.83
0.88
30
37
15
16
15
21
0.02
0.025
1.1
1.0
−
−
−
−
−
−
−
−
mC
Vdc
ns
Symbol
Polarity
Min
Typ
Max
Unit
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
12
I D, DRAIN CURRENT (AMPS)
10
8
6
4
2
0
0
V
GS
= 1.5 V
10 V
2.5 V
4.5 V
3.2 V
2.0 V
−I
D,
DRAIN CURRENT (AMPS)
T
J
= 25°C
1.8 V
4
P−Channel
V
GS
=
−2.1
V
V
GS
=
−10
V
V
GS
=
−4.5
V
V
GS
=
−2.5
V
T
J
= 25°C
V
GS
=
−1.9
V
3
2
V
GS
=
−1.7
V
1
V
GS
=
−1.5
V
0
0.25
0.5
0.75
1
1.25
1.5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1.75
0
2
4
6
8
10
−V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. On−Region Characteristics
12
10
8
6
4
2
0
0.5
100°C
25°C
T
J
=
−55°C
1
1.5
2
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
2.5
−I
D,
DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
V
DS
≥
10 V
5
V
DS
≥
−10
V
4
3
2
1
0
T
J
= 25°C
T
J
= 100°C
1
1.5
T
J
= 55°C
2
2.5
3
−V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. Transfer Characteristics
Figure 4. Transfer Characteristics
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3
NTMD2C02R2
TYPICAL ELECTRICAL CHARACTERISTICS
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
N−Channel
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
2
4
6
8
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
I
D
= 6.0 A
T
J
= 25°C
P−Channel
0.2
T
J
= 25°C
0.15
0.1
0.05
0
2
4
6
8
−V
GS,
GATE−TO−SOURCE VOLTAGE (VOLTS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
Figure 5. On−Resistance versus
Gate−To−Source Voltage
0.05
T
J
= 25°C
0.04
V
GS
= 2.5 V
0.03
4.5 V
Figure 6. On−Resistance versus
Gate−To−Source Voltage
0.12
T
J
= 25°C
0.1
V
GS
=
−2.7
V
0.08
V
GS
=
−4.5
V
0.06
0.02
0.01
1
3
5
7
9
I
D
, DRAIN CURRENT (AMPS)
11
13
0.04
1
1.5
2
2.5
3
3.5
4
4.5
−I
D,
DRAIN CURRENT (AMPS)
Figure 7. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.6
1.4
1.2
1
0.8
0.6
−50
I
D
= 6.0 A
V
GS
= 4.5 V
R
DS(on)
, DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
Figure 8. On−Resistance versus Drain Current
and Gate Voltage
1.6
1.4
1.2
1
0.8
0.6
−50
I
D
=
−2.4
A
V
GS
=
−4.5
V
−25
0
25
50
75
100 125
T
J
, JUNCTION TEMPERATURE (°C)
150
−25
0
25
50
75
100
125
T
J,
JUNCTION TEMPERATURE (°C)
150
Figure 9. On−Resistance Variation with
Temperature
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4
Figure 10. On−Resistance Variation with
Temperature
NTMD2C02R2
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
1000
100
10
1
0.1
0.01
V
GS
= 0 V
T
J
= 125°C
100°C
1000
V
GS
= 0 V
−I
DSS,
LEAKAGE (nA)
100
10
1
0.1
T
J
= 125°C
T
J
= 100°C
T
J
= 25°C
P−Channel
I DSS , LEAKAGE (nA)
25°C
4
8
12
16
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
20
0.01
0
4
8
12
16
−V
DS,
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
20
Figure 11. Drain−To−Source Leakage
Current versus Voltage
Figure 12. Drain−To−Source Leakage
Current versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figures 17 and 18) show how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figures is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
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