Logic Gates Quad 2-Input OR Gate
| Parameter Name | Attribute value |
| Brand Name | Fairchild Semiconductor |
| Is it lead-free? | Lead free |
| Is it Rohs certified? | conform to |
| Maker | Fairchild |
| Parts packaging code | SOIC |
| package instruction | 0.150 INCH, LEAD FREE, MS-012, SOIC-14 |
| Contacts | 14 |
| Manufacturer packaging code | 14LD,SOIC,JEDEC MS-012, .150\", NARROW BODY |
| Reach Compliance Code | compliant |
| ECCN code | EAR99 |
| Samacsys Description | Fairchild Semiconductor 74LCX32M, OR Quad 2 Input OR, 2 → 3.6 V, 14-Pin SOIC |
| series | LVC/LCX/Z |
| JESD-30 code | R-PDSO-G14 |
| JESD-609 code | e3 |
| length | 8.6235 mm |
| Load capacitance (CL) | 50 pF |
| Logic integrated circuit type | OR GATE |
| MaximumI(ol) | 0.024 A |
| Humidity sensitivity level | 1 |
| Number of functions | 4 |
| Number of entries | 2 |
| Number of terminals | 14 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | -40 °C |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | SOP |
| Encapsulate equivalent code | SOP14,.25 |
| Package shape | RECTANGULAR |
| Package form | SMALL OUTLINE |
| method of packing | RAIL |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 3.3 V |
| Prop。Delay @ Nom-Sup | 5.5 ns |
| propagation delay (tpd) | 6.6 ns |
| Certification status | Not Qualified |
| Schmitt trigger | NO |
| Maximum seat height | 1.753 mm |
| Maximum supply voltage (Vsup) | 3.6 V |
| Minimum supply voltage (Vsup) | 2 V |
| Nominal supply voltage (Vsup) | 2.5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | INDUSTRIAL |
| Terminal surface | Matte Tin (Sn) |
| Terminal form | GULL WING |
| Terminal pitch | 1.27 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 3.9 mm |
| Base Number Matches | 1 |
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