MC100LVEL58
3.3V ECL 2:1 Multiplexer
Description
The MC100LVEL58 is a 2:1 multiplexer. The device is pin and
functionally equivalent to the EL58 and works from a 3.3 V supply.
With AC performance similar to the EL58 device, the LVEL58 is ideal
for low voltage applications which require the ultimate in AC
performance.
Features
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MARKING
DIAGRAMS*
8
1
SO−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
KVL58
ALYW
G
1
•
440 ps Typical Propagation Delays
•
ESD Protection: > 4 kV Human Body Model,
•
•
•
•
•
•
•
•
•
•
>200 V Machine Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−3.8
V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at V
EE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 93 devices
Pb−Free Packages are Available
8
KV58
ALYWG
G
1
1
DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
August, 2008
−
Rev. 6
1
Publication Order Number:
MC100LVEL58/D
4H M
G
G
4
MC100LVEL58
NC
1
8
V
CC
Da
2
1
MUX
7
Q
Db
3
0
6
Q
SEL
4
5
V
EE
Figure 1. Logic Diagram and Pinout Assignment
Table 1. PIN DESCRIPTION
PIN
Da, Db
Q, Q
SEL
V
CC
V
EE
NC
EP
FUNCTION
ECL Data Inputs
ECL Differential Data Outputs
ECL Select Input
Positive Supply
Negative Supply
No Connect
(DFN8 only) Thermal exposed pad must be connected
to a sufficient thermal conduit. Electrically connect to
the most negative supply (GND) or leave unconnected,
floating open.
Table 2. TRUTH TABLE
SEL
H
L
Data
a
b
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Pb
Pb−Free
(Note 1)
DFN8
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
8 SOIC
8 SOIC
8 SOIC
8 TSSOP
8 TSSOP
8 TSSOP
DFN8
DFN8
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
−40
to +85
−65
to +150
190
130
41 to 44
±
5%
185
140
41 to 44
±
5%
129
84
265
265
35 to 40
Units
V
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C/W
Thermal Resistance (Junction−to−Case)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power)
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2
MC100LVEL58
Table 4. LVPECL DC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
2215
1470
2135
1490
Min
Typ
21
2295
1605
Max
28
2420
1745
2420
1825
150
0.5
2275
1490
2135
1490
Min
25°C
Typ
21
2345
1595
Max
28
2420
1680
2420
1825
150
0.5
2275
1490
2135
1490
Min
85°C
Typ
23
2345
1595
Max
30
2420
1680
2420
1825
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
3. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
Table 5. LVNECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 4)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
−1085
−1830
−1165
−1810
Min
Typ
21
−1005
−1695
Max
28
−880
−1555
−880
−1475
150
0.5
−1025
−1810
−1165
−1810
Min
25°C
Typ
21
−955
−1705
Max
28
−880
−1620
−880
−1475
150
0.5
−1025
−1810
−1165
−1810
Min
85°C
Typ
23
−955
−1705
Max
30
−880
−1620
−880
−1475
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
5. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
Table 6. AC CHARACTERISTICS
V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 6)
−40°C
Symbol
f
max
t
PLH
t
PHL
t
r
t
f
Characteristic
Maximum Toggle Frequency
Propagation
Delay
Output Rise/Fall Times
(20%
−
80%)
D to Q
SEL to Q
Q
340
350
100
Min
Typ
TBD
435
455
560
570
320
350
360
100
Max
Min
25°C
Typ
TBD
440
460
570
580
320
370
380
100
Max
Min
85°C
Typ
TBD
450
470
590
600
320
Max
Unit
GHz
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. V
EE
can vary
±0.3
V.
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3
MC100LVEL58
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
CC
−
3.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
−
Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
MC100LVEL58D
MC100LVEL58DG
MC100LVEL58DR2
MC100LVEL58DR2G
MC100LVEL58DT
MC100LVEL58DTG
MC100LVEL58DTR2
MC100LVEL58DTR2G
MC100LVEL58MNR4G
Package
SO−8
SO−8
(Pb−Free)
SO−8
SO−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
DFN8
(Pb−Free)
Shipping
†
98 Units / Rail
98 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
100 Units / Rail
100 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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4
MC100LVEL58
PACKAGE DIMENSIONS
SO−8 NB
CASE 751−07
ISSUE AH
−X−
A
8
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
_
8
_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
_
8
_
0.010
0.020
0.228
0.244
B
1
S
4
0.25 (0.010)
M
Y
M
−Y−
G
K
C
−Z−
H
D
0.25 (0.010)
M
SEATING
PLANE
N
X 45
_
0.10 (0.004)
M
J
Z Y
S
X
S
DIM
A
B
C
D
G
H
J
K
M
N
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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