EP3C5F256C6N datasheet, PDF - EEWORLD Datasheet

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EP3C5F256C6N: DescriptionFPGA - Field Programmable Gate Array FPGA - Cyclone III 321 LABs 182 IOs; CategoryProgrammable logic devices Programmable logic; File Size300KB，14 Pages; ManufacturerAltera (Intel); Environmental Compliance

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EP3C5F256C6N Overview

FPGA - Field Programmable Gate Array FPGA - Cyclone III 321 LABs 182 IOs

EP3C5F256C6N Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Altera (Intel)
Parts packaging code	BGA
package instruction	17 X 17 MM, 1.55 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256
Contacts	256
Reach Compliance Code	unknown
ECCN code	EAR99
maximum clock frequency	472.5 MHz
JESD-30 code	R-PBGA-B256
JESD-609 code	e1
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	5136
Number of entries	182
Number of logical units	5136
Output times	182
Number of terminals	256
Maximum operating temperature	85 °C
Minimum operating temperature
organize	5136 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.55 mm
Maximum supply voltage	1.25 V
Minimum supply voltage	1.15 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	17 mm

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1. Cyclone III Device Family Overview

July 2012

CIII51001-2.4

Cyclone

III device family offers a unique combination of high functionality, low

power and low cost. Based on Taiwan Semiconductor Manufacturing Company

(TSMC) low-power (LP) process technology, silicon optimizations and software

features to minimize power consumption, Cyclone III device family provides the ideal

solution for your high-volume, low-power, and cost-sensitive applications. To address

the unique design needs, Cyclone III device family offers the following two variants:

■

Cyclone III—lowest power, high functionality with the lowest cost

Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and

0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power

consumption, Cyclone III device family makes it easier for you to meet your power

budget. Cyclone III LS devices are the first to implement a suite of security features at

the silicon, software, and intellectual property (IP) level on a low-power and

high-functionality FPGA platform. This suite of security features protects the IP from

tampering, reverse engineering and cloning. In addition, Cyclone III LS devices

support design separation which enables you to introduce redundancy in a single

chip to reduce size, weight, and power of your application.

This chapter contains the following sections:

■

“Cyclone III Device Family Features” on page 1–1

“Cyclone III Device Family Architecture” on page 1–6

“Reference and Ordering Information” on page 1–12

Cyclone III Device Family Features

Cyclone III device family offers the following features:

Lowest Power FPGAs

■

Lowest power consumption with TSMC low-power process technology and

Altera

power-aware design flow

Low-power operation offers the following benefits:

■

Extended battery life for portable and handheld applications

Reduced or eliminated cooling system costs

Operation in thermally-challenged environments

■

Hot-socketing operation support

are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its

semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and

services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service

described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying

on any published information and before placing orders for products or services.

ISO

9001:2008

Registered

Cyclone III Device Handbook

Volume 1

July 2012

EP3C5F256C6N Related Products

	EP3C5F256C6N	EP3CLS70F780C7N	EP3C55F484C8N	EP3C40F780C8N	EP3C80U484C8	EP3C40U484I7	EP3CLS70U484C8N	EP3C10F256C8N	EP3C40F324C8N	EP3C25F324I7N
Description	FPGA - Field Programmable Gate Array FPGA - Cyclone III 321 LABs 182 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 4388 LABs 429 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 3491 LABs 327 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 2475 LABs 535 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 5079 LABs 295 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 2475 LABs 331 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 4388 LABs 294 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 645 LABs 182 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 2475 LABs 195 IOs	FPGA - Field Programmable Gate Array FPGA - Cyclone III 1539 LABs 215 IOs
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Contains lead	Contains lead	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	incompatible	incompatible	conform to	conform to	conform to	conform to
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	17 X 17 MM, 1.55 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256	LEAD FREE, FBGA-780	23 X 23 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484	29 X 29 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-780	19 X 19 MM, 0.80 MM PITCH, UBGA-484	19 X 19 MM, 0.80 MM PITCH, UBGA-484	LEAD FREE, UBGA-484	17 X 17 MM, 1.55 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-256	19 X 19 MM, 2.20 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-324	BGA, BGA324,18X18,40
Contacts	256	780	484	780	484	484	484	256	324	324
Reach Compliance Code	unknown	unknown	unknown	unknown	not_compliant	not_compliant	unknown	unknown	unknown	unknown
ECCN code	EAR99	3A991	3A991	3A001.A.7.A	3A991	3A001.A.7.A	3A991	EAR99	3A001.A.7.A	3A991
maximum clock frequency	472.5 MHz	450 MHz	472.5 MHz	472.5 MHz	472.5 MHz	472.5 MHz	450 MHz	472.5 MHz	472.5 MHz	472.5 MHz
JESD-30 code	R-PBGA-B256	S-PBGA-B780	R-PBGA-B484	R-PBGA-B780	S-PBGA-B484	S-PBGA-B484	S-PBGA-B484	R-PBGA-B256	R-PBGA-B324	R-PBGA-B324
JESD-609 code	e1	e1	e1	e1	e0	e0	e1	e1	e1	e1
length	17 mm	29 mm	23 mm	29 mm	19 mm	19 mm	19 mm	17 mm	19 mm	19 mm
Humidity sensitivity level	3	3	3	3	3	3	3	3	3	3
Configurable number of logic blocks	5136	70208	55856	39600	81264	39600	70208	10320	39600	24624
Number of entries	182	413	327	535	295	331	413	182	195	215
Number of logical units	5136	70208	55856	39600	81264	39600	70208	10320	39600	24624
Output times	182	413	327	535	295	331	413	182	195	215
Number of terminals	256	780	484	780	484	484	484	256	324	324
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	100 °C	85 °C	85 °C	85 °C	100 °C
organize	5136 CLBS	70208 CLBS	55856 CLBS	39600 CLBS	81264 CLBS	39600 CLBS	70208 CLBS	10320 CLBS	39600 CLBS	24624 CLBS
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	BGA	BGA	BGA	FBGA	FBGA	FBGA	LBGA	BGA	BGA
Encapsulate equivalent code	BGA256,16X16,40	BGA780,28X28,40	BGA484,22X22,40	BGA780,28X28,40	BGA484,22X22,32	BGA484,22X22,32	BGA484,22X22,32	BGA256,16X16,40	BGA324,18X18,40	BGA324,18X18,40
Package shape	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, LOW PROFILE	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	245	260	245	220	220	260	260	260	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.55 mm	2.4 mm	2.6 mm	3.5 mm	2.05 mm	2.05 mm	2.05 mm	1.55 mm	2.2 mm	2.2 mm
Maximum supply voltage	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V
Minimum supply voltage	1.15 V	1.15 V	1.15 V	1.15 V	1.15 V	1.15 V	1.15 V	1.15 V	1.15 V	1.15 V
Nominal supply voltage	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	INDUSTRIAL	OTHER	OTHER	OTHER	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	0.8 mm	0.8 mm	0.5 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40	40	40	30	30	40	30	40	40
width	17 mm	29 mm	23 mm	29 mm	19 mm	19 mm	19 mm	17 mm	19 mm	19 mm
Maker	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	Altera (Intel)	-
Base Number Matches	-	-	1	1	1	1	-	-	1	1

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