HI-3596, HI-3597, HI-3598, HI-3599
August, 2013
Octal ARINC 429 Receivers
with Label Recognition and SPI Interface
•
32
nd
bit can be data or parity
•
Low Power
•
Industrial & extended temperature ranges
GENERAL DESCRIPTION
The HI-359x family from Holt Integrated Circuits are sili-
con gate CMOS ICs for interfacing up to eight ARINC
429 receive buses to a high-speed Serial Peripheral
Interface (SPI) enabled microcontroller. Each receiver
has user-programmable label recognition for up to 16
labels, a four-word data buffer (FIFO), and an on-chip
analog line receiver. Receive FIFO status can be moni-
tored using the programmable external interrupt pins,
or by polling the status register. Other features include
the ability to switch the bit-signifiance of the ARINC 429
label and to recognize the 32
nd
received ARINC bit as
either data or a parity flag. Some versions provide a digi-
tal transmit channel which can be utilized with an exter-
nal line driver such as HI-8570 to relay information from
multiple sources, for example sensors, to a single col-
lection point such as a flight computer and can also be
configured as a loopback test register for each receive
channel. Versions are also available with different input
resistance values to provide flexibility when using exter-
nal lightning protection circuitry. The SPI and all control
signals are CMOS and TTL compatible and support
3.3V or 5V operation.
The HI-3596 and HI-3598 are full featured parts. The
HI-3597 and HI-3599 give the user the option of utilizing
a smaller 24-pin SOIC package with very little trade off in
features. In this case, a global interrupt flag is provided
instead of individual external FIFO interrupt pins. The
HI-3597 is identical to the HI-3599 except that it offers
the digital transmit feature and seven receive channels.
PIN CONFIGURATION (TOP VIEW)
52 - FLAG1
51 - FLAG2
50 - FLAG3
49 - FLAG4
48 - FLAG5
47 - FLAG6
46 - FLAG7
45 - FLAG8
44 - VDD
43 - FLAG
42 - RIN8B
41 - RIN8B-40
40 - RIN8A-40
ACLK - 1
SCK - 2
__
CS - 3
SI - 4
SO - 5
MR - 6
TX1 - 7
TX0 - 8
RIN1A - 9
RIN1A-40 - 10
RIN1B-40 - 11
RIN1B - 12
- 13
HI-3598PQI
&
HI-3598PQT
39 - RIN8A
38 - RIN7B
37 - RIN7B-40
36 - RIN7A-40
35 - RIN7A
34 - RIN6B
33 - RIN6B-40
32 - RIN6A-40
31 - RIN6A
30 - RIN5B
29 - RIN5B-40
28 - RIN5A-40
27 - RIN5A
HI-3598 Full function, full pin-out version
52 - Pin Plastic Quad Flat Pack (PQFP)
ACLK - 1
SCK - 2
CS - 3
SI - 4
SO - 5
TX1 - 6
TX0 - 7
RIN2A - 8
RIN2B - 9
RIN3A - 10
RIN3B - 11
GND - 12
24 - VDD
23 - FLAG
22 - RIN8B
21 - RIN8A
20 - RIN7B
19 - RIN7A
18 - RIN6B
17 - RIN6A
16 - RIN5B
15 - RIN5A
14 - RIN4B
13 - RIN4A
FEATURES
•
ARINC 429 compliant
•
Up to 8 independent receive channels
•
Digital transmit channel (except HI-3599)
•
3.3V or 5.0V logic supply operation
•
On-chip analog line receivers connect directly to
ARINC 429 bus
•
Programmable label recognition for 16 labels per
channel
•
Independent data rate selection for each receiver
•
Four-wire SPI interface
•
Label bit-order control
HI-3597 minimum footprint, reduced pin-out version
24 - Pin Plastic Small Outline package (SOIC)
(See
page 13 for additional package pin configurations)
DS3598 Rev. D
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
RIN2A - 14
RIN2A-40 - 15
RIN2B-40 - 16
RIN2B - 17
RIN3A - 18
RIN3A-40 - 19
RIN3B-40 - 20
RIN3B - 21
GND - 22
RIN4A - 23
RIN4A-40 - 24
RIN4B-40 - 25
RIN4B - 26
HI-3597
PSI
&
HI-3597
PST
08/13
HI-3596, HI-3597, HI-3598, HI-3599
BLOCK DIAGRAMS
HI-3596 & HI-3598
ACLK
SCK
CS
SI
SO
Transmit Register
TX1, TX0
Ch 8
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Channel 1
SPI
Interface
Status Register
FLAG
VDD
MR
Control Register
BUS 8
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
ARINC 429
Bus 1
16 Label
Filter
Memory
{
RIN1A
RIN1B
RIN1A-40
RIN1B-40
40 Kohm
40 Kohm
ARINC 429
valid word
checker
ARINC 429
Line Receiver
GND
Label
Filter
ARINC 429
Received
Data FIFO
(4 words)
FLAG8
FLAG7
FLAG6
FLAG5
FLAG4
FLAG3
FLAG2
FLAG1
NOTE:
RIN1A & RIN1B available only on HI-3596
RIN1A-40 & RIN1B-40 available only on HI-3596-40
HI-3597 & HI-3599 (24-pin versions)
ACLK
SCK
CS
SI
SO
Transmit Register
TX1, TX0
(HI-3597 only)
Ch 8
Ch 7
Ch 6
Ch 5
Ch 4
Ch 3
Ch 2
Channel 1
SPI
Interface
VDD
Status Register
FLAG
BUS 8
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
ARINC 429
Bus 1
Control Register
16 Label
Filter
Memory
{
RIN1A*
RIN1B*
40 Kohm
40 Kohm
*NOTE:
RIN1A & RIN1B
are not available
on HI-3597
ARINC 429
Line Receiver
The 40 Kohm resistors are shorted on the
HI-3597-40 and HI-3599-40
ARINC 429
valid word
checker
Label
Filter
ARINC 429
Received
Data FIFO
(4 words)
GND
Figure 1.
Block Diagrams
HOLT INTEGRATED CIRCUITS
2
HI-3596, HI-3597, HI-3598, HI-3599
PIN DESCRIPTIONS
Table 1. Pin Descriptions
Pin
VDD
GND
CS
SCK
SI
SO
ACLK
RIN1A* - RIN8A
RIN1B* - RIN8B
RIN1A-40* - RIN8A-40
RIN1B-40* - RIN8B-40
FLAG1 - FLAG8
FLAG
TX1
TX0
MR
Function Description
POWER
POWER
INPUT
INPUT
INPUT
3.3V or 5.0V power supply
Chip 0V supply
Chip select. Data is shifted into SI and out of SO when
CS is low
SPI Clock. Data is shifted into or out of the SPI interface
using SCK
SPI interface serial data input
3596 3597 3598 3599
X
X
X
X
X
X
X
Std
Std
-40
-40
X
X
X
X
X
X
X
X
X
X
X
X
Std
Std
-40
-40
-
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Std
Std
-40
-40
-
X
-
-
-
OUTPUT SPI interface serial data output
INPUT
ARINC
INPUT
ARINC
INPUT
ARINC
INPUT
ARINC
INPUT
OUTPUT
Master 1 MHz timing reference for the ARINC 429
receiver and transmitter
ARINC receiver positive input. Direct connection to
ARINC 429 bus
ARINC receiver negative input. Direct connection to
ARINC 429 bus
Alternate ARINC receiver positive input. Requires
external 40KΩ resistor
Alternate ARINC receiver negative input. Requires
external 40KΩ resistor
Goes high when ARINC 429 receiver FIFO is not empty
(CR1=0), or full (CR1=1)
OUTPUT Logical OR of FLAG1 through FLAG8
OUTPUT ARINC 429 test word ONE state serial output pin
OUTPUT ARINC 429 test word ZERO state serial output pin
INPUT
Hardware active high Master Reset. Clears all
receivers and FIFOs. Does not affect Control Register
contents.
* NOTE:
RIN1A & RIN1B are not available on HI-3597
HOLT INTEGRATED CIRCUITS
3
HI-3596, HI-3597, HI-3598, HI-3599
INSTRUCTIONS
Instruction op codes are used to read, write and con-
figure the HI-359x devices. The instruction format is
illustrated in Figure 2. When CS goes low, the next 8
clocks at the SCK pin shift an instruction op code into
the decoder, starting with the first rising edge. The op
code is fed into the SI pin, most significant bit first.
For write instructions, the most significant bit of the data
word must immediately follow the instruction op code
and is clocked into its register on the next rising SCK
edge. Data word length varies depending on word type
written: 16-bit Control Register writes, 32-bit transmit
register writes or 128-bit writes to a channel’s label-
matching enable/disable memory.
For read instructions, the most significant bit of the
requested data word appears at the SO pin after the last
op code bit is clocked into the decoder, at the next fall-
ing SCK edge. As in write instructions, the data field
bit-length varies with read instruction type.
Channel-specific instructions use the upper four bits to
specify an ARINC 429 receiver channel, 1-8 hex. The
Table 2.
Defined Instructions
ARINC OP CODE
Channel
Hex
X
1h - 8h
1h - 8h
1h - 8h
1h - 8h
1h - 8h
X
X
X
X
X
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah - Fh
DATA
FIELD
None
128 bits
128 bits
32 bits
16 bits
16 bits
16 bits
None
32 bits
32 bits
None
Description
Instruction not implemented. No operation.
Load label values to label memory. The data field consists of 16, 8-bit labels.
If fewer than 16 labels are needed for the application, the memory must be
padded with redundant (duplicate) label values.
Read the contents of the label memory for this channel.
Read an ARINC word from the receive FIFO for this channel. If the FIFO is
empty all zeros will be read.
Load the specified channel’s Control Register and clear that channel’s FIFO.
Read the specified channel’s Control Register.
Read the Status Register.
Master Reset (All channels).
Load the Transmit Register (High-speed data rate). This can also be used as
a test word for each receiver (Loopback self-test).
Load the Transmit Register (Low-speed data rate). This can also be used
as a test word for each receiver (Loopback self-test).
Instruction not implemented. No operation.
lower four bits specify the op code, described in Table
2. The four channel assignment bits are “don’t care” for
instructions that are not channel-specific, such as Mas-
ter Reset.
ARINC 429
Channel
OP Code
MSB
7
6
5
4
3
2
1
0
LSB
SPI INSTRUCTION FORMAT
Example:
CS
SCK
SI
MSB
LSB MSB
LSB
One SPI Instruction
op code 14 hex
data field 0232 hex
ie: Load channel 1 control register with 0232 hex
Figure 2. SPI Instruction Format
HOLT INTEGRATED CIRCUITS
4
HI-3596, HI-3597, HI-3598, HI-3599
FUNCTIONAL DESCRIPTION
Control Word Register
Each HI-359x receive channel is assigned a 16-bit
Control Register which configures that receiver. Con-
trol Register bits CR15 - CR0 are loaded from a 16-bit
data value appended to SPI instruction n4 hex, where
“n” is the channel number 1-8 hex. Writing to the Con-
trol Register also clears the data FIFO for that channel.
The Control Register contents may be read using SPI
instruction n5 hex. Table 3 summarizes the Control Reg-
ister bits functions.
Table 3. Control Register Bits Functions
CR Bit
CR0
(LSB)
Status Register
The HI-359x devices have a single 16-bit Status Reg-
ister which is read to determine status for the eight
received data FIFOs. The Status Register is read using
SPI instruction n6 hex. Table 4 summarizes the Status
Register bits functions.
Table 4. Status Register Bits Functions
CR Bit
Function
State
0
Description
Receiver 1 FIFO contains valid data.
Resets to Zero when all data has been
read. FLAG pin reflects the state of
this bit when CR1=”0”
Receiver 1 FIFO is empty
Receiver 2 FIFO contains valid data.
Receiver 2 FIFO is empty
:
:
:
:
Receiver 8 FIFO contains valid data.
Receiver 8 FIFO is empty
Receiver 1 FIFO not full. FLAG pin
reflects the state of this bit when
CR1=”1”
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within one
ARINC word period.
Receiver 2 FIFO not full.
Receiver 2 FIFO full.
:
:
:
:
Receiver 8 FIFO not full.
Receiver 8 FIFO full.
Function
Receiver
Data Rate
Select
State
0
1
0
1
0
1
0
Description
Data rate = ACLK/10 (ARINC 429
High-Speed)
Data rate = ACLK/80 (ARINC 429
Low-Speed)
FLAG goes high when receive FIFO is
not empty (Contains at least one word)
FLAG goes high when receive FIFO
is full
Label recognition disabled
Label recognition enabled
Normal Operation
Reset this receiver (Clear receiver
logic and FIFO). The receive channel
is disabled if CR3 is left high
Receiver parity check disabled
Receiver odd parity check enabled
Receiver’s inputs are connected to the
Transmit Register serial data output.
Normal operation
Receiver Decoder Disabled
ARINC bits 10 and 9 must match CR7
and CR8
If receiver decoder is enabled, the
ARINC bit 10 must match this bit
If receiver decoder is enabled, the
ARINC bit 9 must match this bit
Label bit order reversed (See Table 5)
Label bit order same as received (See
Table 5)
Control register read returns “0” for
these bits
SR0
(LSB)
Receiver 1
FIFO Empty
1
Receiver 2
FIFO Empty
Receiver 3
to
Receiver 7
FIFO Empty
Receiver 8
FIFO Empty
0
1
:
:
:
:
0
1
0
SR8
Receiver 1
FIFO Full
1
0
1
:
:
:
:
0
1
SR1
CR1
RFLAG
Definition
SR2
to
SR6
CR2
Enable
Label
Recognition
SR7
CR3
Reset
Receiver
1
0
1
0
1
0
1
-
-
0
1
CR4
Receiver
Parity Check
Enable
SR9
Receiver 2
FIFO Full
Receiver 3
to
Receiver 7
FIFO Full
Receiver 8
FIFO Full
CR5
Self-Test
(Loopback)
SR10
to
SR14
SR15
(MSB)
CR6
Receiver
Decoder
CR7
CR8
-
-
ARINC
Label Bit
Order
CR9
CR10
to
CR15
(MSB)
Not Used
X
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