EPM9320LI84-20 datasheet, PDF - EEWORLD Datasheet

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EPM9320LI84-20: DescriptionCPLD - Complex Programmable Logic Devices CPLD - MAX 9000 320 Macro 60 IOs; CategoryProgrammable logic devices Programmable logic; File Size275KB，47 Pages; ManufacturerAltera (Intel)

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EPM9320LI84-20 Overview

CPLD - Complex Programmable Logic Devices CPLD - MAX 9000 320 Macro 60 IOs

EPM9320LI84-20 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	LCC
package instruction	PLASTIC, LCC-84
Contacts	84
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	484 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency	100 MHz
In-system programmable	YES
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
JTAG BST	YES
length	29.3116 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	60
Number of macro cells	320
Number of terminals	84
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 60 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220
power supply	3.3/5,5 V
Programmable logic type	EE PLD
propagation delay	23 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	29.3116 mm
Base Number Matches	1

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Includes

MAX 9000A

MAX 9000

Programmable Logic

Device Family

Data Sheet

June 2003, ver. 6.5

Features...

■

High-performance CMOS EEPROM-based programmable logic

devices (PLDs) built on third-generation Multiple Array MatriX

(MAX

) architecture

5.0-V in-system programmability (ISP) through built-in IEEE Std.

1149.1 Joint Test Action Group (JTAG) interface

Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE

Std. 1149.1-1990

High-density erasable programmable logic device (EPLD) family

ranging from 6,000 to 12,000 usable gates (see

Table 1)

10-ns pin-to-pin logic delays with counter frequencies of up to

144 MHz

Fully compliant with the peripheral component interconnect Special

Interest Group’s (PCI SIG)

PCI Local Bus Specification, Revision 2.2

Dual-output macrocell for independent use of combinatorial and

registered logic

FastTrack

Interconnect for fast, predictable interconnect delays

Input/output registers with clear and clock enable on all I/O pins

Programmable output slew-rate control to reduce switching noise

MultiVolt

™

I/O interface operation, allowing devices to interface with

3.3-V and 5.0-V devices

Configurable expander product-term distribution allowing up to 32

product terms per macrocell

Programmable power-saving mode for more than 50% power

reduction in each macrocell

Table 1. MAX 9000 Device Features

Feature

Usable gates

Flipflops

Macrocells

Logic array blocks (LABs)

Maximum user I/O pins

PD1

(ns)

FSU

(ns)

FCO

(ns)

CNT

(MHz)

EPM9320

EPM9320A

6,000

484

320

168

3.0

4.5

144

EPM9400

8,000

580

400

159

118

EPM9480

10,000

676

480

175

3.0

4.8

144

EPM9560

EPM9560A

12,000

772

560

216

3.0

4.8

144

Altera Corporation

DS-M9000-6.5

EPM9320LI84-20 Related Products

	EPM9320LI84-20	EPM9560ABC356-10	EPM9560ARC208-10N	EPM9320LC84-15	EPM9560RC240-15	EPM9560ARC240-10N
Description	CPLD - Complex Programmable Logic Devices CPLD - MAX 9000 320 Macro 60 IOs	CPLD - Complex Programmable Logic Devices CPLD - MAX 9000 560 Macro 216 IOs	Multilayer Ceramic Capacitors MLCC - SMD/SMT 10uF 20% 10Volts	Modulator / Demodulator Wideband Integ Demod with PLL and VCO	CPLD - Complex Programmable Logic Devices CPLD - MAX 9000 560 Macro 191 IOs	CPLD - Complex Programmable Logic Devices CPLD - MAX 9000 560 Macro 191 IOs
Is it lead-free?	Contains lead	Contains lead	Lead free	Contains lead	Contains lead	Lead free
Is it Rohs certified?	incompatible	incompatible	conform to	incompatible	incompatible	conform to
Parts packaging code	LCC	BGA	QFP	LCC	QFP	QFP
package instruction	PLASTIC, LCC-84	BGA-356	FQFP,	PLASTIC, LCC-84	POWER, RQFP-240	FQFP,
Contacts	84	356	208	84	240	240
Reach Compliance Code	unknown	not_compliant	compliant	unknown	unknown	compliant
Other features	484 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	560 MACROCELLS; 35 LABS; 772 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	560 MACROCELLS; 35 LABS; 772 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	484 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	772 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	560 MACROCELLS; 35 LABS; 772 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency	100 MHz	144.9 MHz	144.9 MHz	117.6 MHz	117.6 MHz	144.9 MHz
JESD-30 code	S-PQCC-J84	S-PBGA-B356	S-PQFP-G208	S-PQCC-J84	S-PQFP-G240	S-PQFP-G240
JESD-609 code	e0	e0	e2	e0	e0	e3
length	29.3116 mm	35 mm	28 mm	29.3116 mm	32 mm	32 mm
Humidity sensitivity level	3	3	3	3	3	3
Number of I/O lines	60	216	153	60	191	191
Number of terminals	84	356	208	84	240	240
Maximum operating temperature	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	0 DEDICATED INPUTS, 60 I/O	0 DEDICATED INPUTS, 216 I/O	0 DEDICATED INPUTS, 153 I/O	0 DEDICATED INPUTS, 60 I/O	0 DEDICATED INPUTS, 191 I/O	0 DEDICATED INPUTS, 191 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	LBGA	FQFP	QCCJ	FQFP	FQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	GRID ARRAY, LOW PROFILE	FLATPACK, FINE PITCH	CHIP CARRIER	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	220	220	245	220	220	245
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	23 ns	11.4 ns	11.4 ns	16 ns	16.6 ns	11.4 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	1.63 mm	4.1 mm	5.08 mm	4.1 mm	4.1 mm
Maximum supply voltage	5.5 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.5 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn63Pb37)	Matte Tin/Copper (Sn/Cu)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	MATTE TIN (472) OVER COPPER
Terminal form	J BEND	BALL	GULL WING	J BEND	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	0.5 mm	1.27 mm	0.5 mm	0.5 mm
Terminal location	QUAD	BOTTOM	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	40	30	30	40
width	29.3116 mm	35 mm	28 mm	29.3116 mm	32 mm	32 mm
In-system programmable	YES	YES	-	YES	YES	-
JTAG BST	YES	YES	-	YES	YES	-
Number of macro cells	320	560	-	320	560	-
Encapsulate equivalent code	LDCC84,1.2SQ	BGA356,26X26,50	-	LDCC84,1.2SQ	HQFP240,1.37SQ,20	-
power supply	3.3/5,5 V	3.3/5,5 V	-	3.3/5,5 V	3.3/5,5 V	-

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