GS1582 Multi-Rate Serializer with Cable Driver, Audio Multiplexer and
ClockCleaner
TM
Key Features
•
•
•
•
HD-SDI, SD-SDI, DVB-ASI transmitter with audio
embedding
Integrated SMPTE 292M and 259M-C compliant cable
driver
Integrated ClockCleaner
™
User selectable video processing features, including:
Generic ancillary data insertion
Support for HVF or EIA/CEA-861 timing input
Automatic standard detection and indication
Enhanced SMPTE 352M payload identifier
generation and insertion
TRS, CRC, ANC data checksum, and line number
calculation and insertion
EDH packet generation and insertion
Illegal code remapping
SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ
→
NRZI encoding
Blanking of input HANC and VANC space
•
User selectable audio processing features, including:
SMPTE 299M and SMPTE 272M-A/C compliant
audio embedding
Support for up to 8 channels
Support for audio group replacement
•
•
•
•
•
•
JTAG test interface
1.8V core and 3.3V charge pump power supply
1.8V and 3.3V digital I/O support
Low power standby mode
Operating temperature range: -20
o
C to +85
o
C
Pb-free, RoHS compliant, 11mm x 11mm 100-ball BGA
package
•
DVB-ASI Serial Digital Interfaces
Description
The GS1582 is the next generation multi-standard
serializer with an integrated cable driver. The device
provides robust parallel to serial conversion, generating a
SMPTE 292M/259M-C compliant serial digital output
signal. The integrated cable driver features an output
disable (high impedance) mode and an adjustable signal
swing. Data input is accepted in 20-bit parallel format or
10-bit parallel format. An associated parallel clock input
must be provided at the appropriate operating frequency;
74.25/74.1758/13.5MHz (20-bit mode) or
148.5/148.352/27MHz (10-bit mode).
The GS1582 features an internal PLL which, if desired, can
be configured for a loop bandwidth below 100kHz. When
used in conjunction with the GO1555 Voltage Controlled
Oscillator, the GS1582 can tolerate well in excess of 300ps
jitter on the input PCLK and still provide output jitter within
SMPTE specifications.
In addition to serializing the input, the GS1582 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
292M/259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization. The device also provides a range of other data
processing functions. All processing features are optional
and may be enabled/disabled via external control pin(s)
and/or host interface programming.
The GS1582 can embed up to 8 channels of audio into the
video data stream in accordance with SMPTE 299M and
SMPTE 272M. The audio input signal formats supported by
the device include AES/EBU and I
2
S serial digital formats
with a 16, 20 or 24 bit sample size and a 48 kHz sample rate.
Additional audio processing features include individual
channel enable, channel swap, group swap, ECC
generation and audio channel status insertion.
Typical power consumption, including the GO1555 VCO, is
500mW. The standby feature allows the power to be
reduced to 125mW. Power may be reduced to less than
1 of 115
Applications
•
SMPTE 292M and SMPTE 259M-C Serial Digital
Interfaces
www.gennum.com
Data Sheet
40117 - 4
GS1582 Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner
TM
December 2011
10mW by also removing the power to the cable driver and
eliminating transitions at the parallel data and clock inputs.
The GS1582 is Pb-free and RoHS compliant.
Functional Block Diagram
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
DVB_ASI
Host Interface
AUDIO_INT
GRP1_EN/DIS
GRP2_EN/DIS
Ain_1/2
Ain_3/4
Ain_5/6
Ain_7/8
ACLK1
ACLK2
WCLK1
WCLK2
F/DE
V/VSYNC
H/HSYNC
TIM_861
DIN[19:0]
PCLK
GSPI
RSET
Input
Mux/
Demux
HANC/
VANC
Blanking
SD/HD
Audio
Embedding
SMPTE 352M
Generation and
Insertion
ANC Data
Insertion
TRS, Line
Number
and CRC
Insertion
EDH
Packet
Insertion
NRZ/NRZI
SMPTE
Scrambler
Mux
Parallel to Serial
Converter
SMPTE
Cable
Driver
SDO
SDO
SDO_EN/DIS
DVB ASI
ENDEC
PhaseDetector/
Chargepump
2.5V
Regulator
LOCKED
ClockCleaner™
VCO
LF
CP_RES
VCO_GND
VCO_VCC
GS1582 Functional Block Diagram
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleaner
TM
Data Sheet
40117 - 4
December 2011
2 of 115
Revision History
Version
4
3
2
1
ECR
157323
151526
150785
146167
PCN
–
52183
51685
–
Date
November
2011
March
2009
October
2008
November
2007
Changes and/or Modifications
Corrected a typo under Default column for Address 422h in
Table 4-44.
Changed Parallel Input Data Hold Time from 2ns to 0.8ns in
Table 2-3: AC Electrical
Characteristics.
Changed
Figure 4-30: GSPI Write Mode Timing.
Converted to a Data Sheet.
Updates to: Note 4 in
Table 2-2 on page 20, Audio Modes of Operation on page 38,
Arbitrary, SMPTE 352M & EDH Packet Detect on page 40, Table 4-3 on page 39, 4.8
Ancillary Data Insertion, Separate Line Mode on page 64, Concatenated Mode on
page 65, Command Word Description on page 79, 4.13 GSPI Host Interface,
Table 4-33, 4.9.3 Video Standard Indication, 2.3 DC Electrical Characteristics, 4.9.4.4
Ancillary Data Checksum Generation and Insertion, Table 2-3: AC Electrical
Characteristics, 4.7.14 Interrupt Control,4.9.4.1 SMPTE 352M Payload Identifier Packet
Insertion, 4.7.9.1 SD Formats
and
4.7.9.2 HD Formats.
Converted to Preliminary Data Sheet. Changes were made in the following areas;
Table 1-1: Pin Descriptions, 2.1 Absolute Maximum Ratings, 2.2 Recommended
Operating Conditions, 2.3 DC Electrical Characteristics, 2.4 AC Electrical
Characteristics, 4.3 SMPTE Mode, 4.3.1 HVF Timing, 4.6 Standby Mode, 4.7.20 Audio
Word Clock, 4.8 Ancillary Data Insertion, 4.8.3 VANC Insertion, 4.9.4.1 SMPTE 352M
Payload Identifier Packet Insertion, 4.9.4.3 EDH Generation and Insertion, 4.11.2 Loop
Filter, 4.11.3 Lock Detect Output, 4.13.1 Command Word Description, Table 4-44: SD
Audio Configuration and Status Registers, Table 4-45: HD Audio Configuration and
Status Registers, 4.15 Device Reset, 5.1 Typical Application Circuit (Part A), 7.1
Package Dimensions, 7.2 Packaging Data, 7.2 Packaging Data, 7.5 Ordering
Information,
Changed pin F4 to RSV and added drive strength values for pin H4, H7, and J9 in
Pin
Assignment
and
Pin Descriptions.
Modified input voltage range parameter in
Absolute Maximum Ratings.
Updated serial output intrinsic jitter value in
AC
Electrical Characteristics.
Added digital input/output circuits in
Section 3.
Added note
to
4.7.20 Audio Word Clock.
New Document.
0
145472
–
June 2007
B
144894
–
April 2007
A
141222
–
March
2007
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleaner
TM
Data Sheet
40117 - 4
December 2011
3 of 115
Contents
1. Pin Out...............................................................................................................................................................9
1.1 Pin Assignment ..................................................................................................................................9
1.2 Pin Descriptions ............................................................................................................................. 10
2. Electrical Characteristics ......................................................................................................................... 19
2.1 Absolute Maximum Ratings ....................................................................................................... 19
2.2 Recommended Operating Conditions .................................................................................... 19
2.3 DC Electrical Characteristics ..................................................................................................... 20
2.4 AC Electrical Characteristics ..................................................................................................... 21
3. Input/Output Circuits ............................................................................................................................... 23
4. Detailed Description.................................................................................................................................. 26
4.1 Functional Overview .................................................................................................................... 26
4.2 Parallel Data Inputs ....................................................................................................................... 26
4.2.1 Parallel Input in SMPTE Mode....................................................................................... 27
4.2.2 Parallel Input in DVB-ASI Mode................................................................................... 27
4.2.3 Parallel Input in Data-Through Mode......................................................................... 27
4.2.4 Parallel Input Clock (PCLK) ............................................................................................ 28
4.3 SMPTE Mode ................................................................................................................................... 29
4.3.1 HVF Timing.......................................................................................................................... 29
4.3.2 CEA 861 Timing.................................................................................................................. 31
4.4 DVB-ASI mode ................................................................................................................................ 35
4.4.1 Control Signal Inputs........................................................................................................ 35
4.5 Data-Through Mode ..................................................................................................................... 36
4.6 Standby Mode ................................................................................................................................. 36
4.7 Audio Multiplexer ......................................................................................................................... 37
4.7.1 Audio Core Configurations ............................................................................................ 37
4.7.2 Audio Detection ................................................................................................................. 38
4.7.3 Audio Modes of Operation ............................................................................................. 38
4.7.4 Audio Packet Delete ......................................................................................................... 40
4.7.5 Arbitrary, SMPTE 352M & EDH Packet Detect......................................................... 40
4.7.6 Audio Packet Multiplexing............................................................................................. 41
4.7.7 Audio Insertion After Video Switching Point .......................................................... 42
4.7.8 Audio Data Packets........................................................................................................... 42
4.7.9 Audio Control Packets ..................................................................................................... 46
4.7.10 Setting Packet DID .......................................................................................................... 48
4.7.11 Audio Group Replacement .......................................................................................... 49
4.7.12 Channel and Group Activation .................................................................................. 51
4.7.13 ECC Error Detection & Correction (HD Mode Only)............................................ 51
4.7.14 Interrupt Control ............................................................................................................. 51
4.7.15 Audio Clocks..................................................................................................................... 51
4.7.16 5-frame Sequence Detection....................................................................................... 52
4.7.17 Audio Input Format........................................................................................................ 53
4.7.18 Audio Channel Status Input ........................................................................................ 56
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleaner
TM
Data Sheet
40117 - 4
December 2011
4 of 115
4.7.19 Audio Crosspoint............................................................................................................. 58
4.7.20 Audio Word Clock .......................................................................................................... 59
4.7.21 GS1582 SD Audio FIFO Block ..................................................................................... 59
4.7.22 Audio Sample Distributions......................................................................................... 60
4.7.23 Audio Mute........................................................................................................................ 63
4.8 Ancillary Data Insertion .............................................................................................................. 63
4.8.1 Ancillary Data Insertion Operating Mode................................................................. 64
4.8.2 HANC Insertion.................................................................................................................. 65
4.8.3 VANC Insertion .................................................................................................................. 66
4.9 Additional Processing Functions .............................................................................................. 66
4.9.1 ANC Data Blanking ........................................................................................................... 66
4.9.2 Automatic Video Standard Detection......................................................................... 66
4.9.3 Video Standard Indication ............................................................................................. 67
4.9.4 Packet Generation and Insertion.................................................................................. 69
4.10 Parallel to Serial Conversion ................................................................................................... 74
4.11 Internal ClockCleaner
TM
PLL .................................................................................................. 75
4.11.1 External VCO.................................................................................................................... 75
4.11.2 Loop Filter.......................................................................................................................... 75
4.11.3 Lock Detect Output......................................................................................................... 76
4.12 Serial Digital Output .................................................................................................................. 77
4.12.1 Output Swing.................................................................................................................... 77
4.13 GSPI Host Interface ..................................................................................................................... 77
4.13.1 Command Word Description ...................................................................................... 79
4.13.2 Data Read and Write Timing ....................................................................................... 79
4.13.3 Configuration and Status Registers........................................................................... 81
4.14 JTAG Test Operation ................................................................................................................ 106
4.15 Device Reset ................................................................................................................................ 108
5. Application Reference Design ............................................................................................................. 109
5.1 Typical Application Circuit (Part A) ....................................................................................... 109
5.2 Typical Application Circuit (Part B) ....................................................................................... 110
6. References & Relevant Standards ....................................................................................................... 111
7. Package & Ordering Information ........................................................................................................ 112
7.1 Package Dimensions ................................................................................................................... 112
7.2 Packaging Data ............................................................................................................................. 113
7.3 Marking Diagram ......................................................................................................................... 113
7.4 Solder Reflow Profile .................................................................................................................. 114
7.5 Ordering Information ................................................................................................................. 114
GS1582 Multi-Rate Serializer with Cable Driver, Audio
Multiplexer and ClockCleaner
TM
Data Sheet
40117 - 4
December 2011
5 of 115
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