STB23NM50N, STF23NM50N
STP23NM50N, STW23NM50N
N-channel 500 V, 0.162
Ω
17 A TO-220, TO-220FP, TO-247, D²PAK
,
MDmesh™ II Power MOSFET
Features
Order codes
STB23NM50N
STF23NM50N
STP23NM50N
STW23NM50N
■
■
■
V
DSS
(@Tjmax)
R
DS(on)
max.
I
D
3
1
2
1
3
2
TO-220FP
550 V
< 0.19
Ω
17 A
TO-220
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
TO-247
2
1
3
3
1
D²PAK
Application
Switching applications
Figure 1.
Internal schematic diagram
Description
These devices are made using the second
generation of MDmesh™ technology. This
revolutionary Power MOSFET associates a new
vertical structure to the company’s strip layout to
yield one of the world’s lowest on-resistance and
gate charge. It is therefore suitable for the most
demanding high efficiency converters.
Table 1.
Device summary
Marking
Package
D²PAK
TO-220FP
23NM50N
TO-220
TO-247
Tube
Packaging
Tape and reel
Order codes
STB23NM50N
STF23NM50N
STP23NM50N
STW23NM50N
May 2011
Doc ID 16913 Rev 4
1/21
www.st.com
21
Contents
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
4
5
6
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/21
Doc ID 16913 Rev 4
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D
I
D
I
DM (2)
P
TOT
V
ISO
dv/dt
(3)
T
stg
T
j
Absolute maximum ratings
Value
Parameter
TO-220, D²PAK TO-247 TO-220FP
Drain-source voltage (V
GS
= 0)
Gate- source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Insulation withstand voltage (RMS) from all
three leads to external heat sink
(t=1 s;T
C
=25 °C)
Peak diode recovery voltage slope
Storage temperature
Max. operating junction temperature
15
-55 to 150
150
17
11
68
125
500
± 25
17
(1)
11
(1)
68
(1)
30
2500
V
V
A
A
A
W
V
V/ns
°C
°C
Unit
1. Limited only by maximum temperature allowed
2. Pulse width limited by safe operating area
3. I
SD
≤
17 A, di/dt
≤
400 A/µs, V
DS
peak
≤
V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
Table 3.
Symbol
Thermal data
Value
Parameter
D²PAK
TO-247
1
30
62.5
50
300
62.5
TO-220
TO-220FP
4.17
°C/W
°C/W
°C/W
°C
Thermal resistance junction-case
max
Thermal resistance junction-pcb
minimum footprint
Thermal resistance junction-
ambient max
Maximum lead temperature for
soldering purpose
Unit
R
thj-case
R
thj-pcb (1)
R
thj-amb
T
l
1. When mounted on 1inch² FR-4 board, 2 oz Cu
Table 4.
Symbol
I
AR
E
AS
Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by Tj Max)
Single pulse avalanche energy
(starting Tj = 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Doc ID 16913 Rev 4
Value
6
254
Unit
A
mJ
3/21
Electrical characteristics
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
2
Electrical characteristics
(T
CASE
=25 °C unless otherwise specified)
Table 5.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On/off states
Parameter
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
= 0)
Gate-body leakage
current (V
DS
= 0)
Gate threshold voltage
Static drain-source on
resistance
Test conditions
I
D
= 1 mA, V
GS
= 0
V
DS
= max rating
V
DS
= max rating, @125 °C
V
GS
= ± 25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 8.5 A
2
3
0.162
Min.
500
1
100
100
4
0.19
Typ.
Max. Unit
V
µA
µA
nA
V
Ω
Table 6.
Symbol
C
iss
C
oss
C
rss
C
oss eq. (1)
Q
g
Q
gs
Q
gd
R
g
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
Test conditions
Min.
Typ.
1330
84
4.8
210
45
7
24
4.6
Max. Unit
pF
pF
pF
pF
nC
nC
nC
Ω
V
DS
= 50 V, f = 1 MHz,
V
GS
= 0
-
-
V
GS
= 0, V
DS
= 0 to 400 V
V
DD
= 400 V, I
D
= 17 A,
V
GS
= 10 V,
(see Figure 18)
f=1 MHz Gate DC Bias=0
Test signal level=20 mV
open drain
-
-
-
-
-
-
1. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DS
4/21
Doc ID 16913 Rev 4
STB23NM50N, STF23NM50N, STP23NM50N, STW23NM50N
Electrical characteristics
Table 7.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
V
DD
= 250 V, I
D
= 17 A
R
G
= 4.7
Ω
V
GS
= 10 V
(see Figure 17)
Min.
Typ.
6.6
19
71
29
Max. Unit
ns
ns
ns
ns
-
-
Table 8.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 17 A, V
GS
= 0
I
SD
= 17 A, di/dt = 100 A/µs
V
DD
= 60 V
(see Figure 22)
I
SD
= 17 A, di/dt = 100 A/µs
V
DD
= 60 V, T
j
= 150 °C
(see Figure 22)
Test conditions
Min
-
-
-
286
3700
26
350
4800
27
Typ.
Max
17
68
1.5
Unit
A
A
V
ns
nC
A
ns
nC
A
V
SD (2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
-
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Doc ID 16913 Rev 4
5/21