OneNAND512/OneNAND1GDDP
FLASH MEMORY
OneNAND SPECIFICATION
Density
512Mb
Part No.
KFG1216Q2M-DEB
KFG1216D2M-DEB
KFG1216U2M-DIB
1Gb
KFH1G16Q2M-DEB
V
CC
(core & IO)
1.8V(1.7V~1.95V)
2.65V(2.4V~2.9V)
3.3V(2.7V~3.6V)
1.8V(1.7V~1.95V)
Temperature
Extended
Extended
Industrial
Extended
PKG
63FBGA(LF)
63FBGA(LF)
63FBGA(LF)
N/A
Version: Ver. 1.4
Date: June 15th, 2005
1
OneNAND512/OneNAND1GDDP
FLASH MEMORY
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
OneNAND
™
‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their
rightful owners.
Copyright
©
2005, Samsung Electronics Company, Ltd
2
OneNAND512/OneNAND1GDDP
Document Title
OneNAND
FLASH MEMORY
Revision History
Revision No. History
0.0
0.0.1
Initial issue.
Draft Date
Jan. 07, 2004
Remark
Preliminary
Preliminary
1. Add the "Invalid block management" and "Error management in read and Jan. 29, 2004
write operation"
2. Add the restriction in addressing for program operation.
3. Add the asynchronous write and latched asynchronous write mode timing
diagram.
4.Define new parameters in asynchronous write mode.
-tCH1 : 10ns, tCH2 : 0ns
1. Add the dual operation diagram.
2. Add the block replacement diagram
1. Edit the block replacement diagram
2. Add the 3.3V product.
1. Excluded Cache Program Operation
2. Added the descriptions for below operations
-. Reset
-. Write Protection
-. Burst Read Latency
-. Dual Operation
-. Invalid block definition and Identification method
-. Error in write or read operation
-. ECC
3. Revised program sequence
4. Some AC parameters are changed.
tACH : 9ns-->7ns, tCES : 7ns-->9ns, tAAVDS : 5ns-->7ns
tDS : 30ns-->10ns, tDH : 0ns-->4ns
5. Define new AC parameter.
tAWES(Address hold time in AVD low case of asynchronous write mode)
Min. 0ns
1. Correct an errata
Ball pitch of package is corrected.
0.5mm --> 0.8mm
2. Edit the timing diagram of burst read wrap around.(Figure 23,24)
Jan. 30, 2004
0.0.2
Preliminary
0.0.3
Feb. 03, 2004
Preliminary
0.1
Feb.11, 2004
Preliminary
0.1.1
Mar.9, 2004
Preliminary
0.2
0.3
1. The specification of 2.7V device is added.
1. The specification of 3.3V device is deleted.
2. Correct some typos.
Mar. 22, 2004
Mar. 31, 2004
Preliminary
Preliminary
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
3
OneNAND512/OneNAND1GDDP
Document Title
OneNAND
FLASH MEMORY
Revision History
Revision No. History
0.4
1. Corrected the errata
2. Added spare assignment information in detail
3. Added NAND array memory map
4. Added manufacturer ID for CS as 00ECh
5. Added stepping ID for CS in version ID register
6. Divided default status of interrupt status register by Warm,Hot reset and
Cold reset
7. Revised Load operation flow chart
8. Revised Program operation flow chart
9. Deleted DBS setting step in Copy-back operation
10. Added OTP description
11. Revised OTP Load and Program flow chart
12. Added INT guidance
13. ECC description is revised
14. Added Data Protection Scheme during Power-down
15. Added DC/AC parameters
Draft Date
June 22, 2004
Remark
Preliminary
1.0
1. Deleted 2.7V product
August 5, 2004
2. Added 2.65V product
3. Added 3.3V product and industrial temperature in 3.3V product
4. Deleted Unlock/Lock BootRAM command
5. Added DBS setting step in Copy-back operation
6. Added 2.65V/3.3V DC parameters
7. Revised tCES from 9ns to 7ns
8. Deleted tOEH in asynchronous read operation
9. Revised NOP from 4 times per each main and spare in a page to 2 times
per sector
10. Revised Write Protection status description
11. Added DDP selection and operation guidance
12. Added 1Gb DDP device ID
13. Added INT bit status in Cold Reset operation
14. Moved Interrupt register setting before inputting command in all flow
charts
15. Revised Dual operation diagrams
16. Added and revised the asynchronous read operation timing diagram
17. Revised the asynchronous write operation timing diagram
18. Added the tREADY parameter in Hot Reset operation
1. Revised standby current for DDP
1. Corrected DDP device ID
2. Excluded Commercial Temperature range
3. Revised Cold Reset timing diagram
4. Added CE and RDY in Warm Reset diagram
5. Excluded Write while Load and Read while Program operation
6. Revised Extended Temperature minimum value from -25 to -30
7. Revised typical tOTP, tLOCK from 300us to 600us
8. Revised max tOTP, tLOCK from 600us to 1000us
9. Revised Icc4, Icc5 test condition
10. Added Endurance and Data Retention
August 26, 2004
October 26, 2004
Final
1.1
1.2
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
4
OneNAND512/OneNAND1GDDP
Document Title
OneNAND
FLASH MEMORY
Revision History
Revision No. History
1.3
1. Deleted Manufacturer ID for ES
2. Excluded bit error case in Load operation
3. Revised tWEA value from max to min
4. Revised tRD1 typical value from 35us to 40us
5. Revised tRD2 typical value from 75us to 85us
6. Added technical note for OneNAND boot sequence
7. Revised Asycnchronous Read timing diagram for CE don’t care mode
8. Revised Asynchronous Write timing diagram for CE don’t care mode
9. Revised Load operation timing diagram for CE don’t care mode
Draft Date
Dec. 16, 2004
Remark
Final
1.4
Jun. 15, 2005
1. Added Copyright Notice in the beginning
2. Corrected Errata
3. Updated Icc2, Icc4, Icc5, Icc6 and I
SB
4. Revised INT pin description
5. Changed default of Manufacturer ID Register with 00ECh
6. Removed "or erase case, refer to the table 3" from descriptions of WB, EB
7. Added OTP erase case NOTE
8. Revised case definitions of Interrupt Status Register
9. Added a NOTE to Command register
10. Added ECClogSector Information table
11. Removed ’data unit based data handling’ from description of Device
Operation
12. Revised description on Warm/Hot/NAND Flash Core Reset
13. Revised Warm Reset Timing
14. Revised description for 4-, 8-, 16-, 32-Word Linear Burst Mode
15. Revised OTP operation description
16. Restored earlier text for OTP Programming
17. Added supplemental explanation for ECC Operation
18. Replaced "read" with "load" in ECC bypass
19. Removed redundant sentance from ECC Bypass Operation
20. Added technical note for INT pin connection guide
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
5
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