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MC14011BCPG

Description
4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14
Categorylogic    logic   
File Size159KB,12 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance  
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MC14011BCPG Overview

4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14

MC14011BCPG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid2014176289
Parts packaging codeDIP
package instructionROHS COMPLIANT, PLASTIC, DIP-14
Contacts14
Reach Compliance Codeunknown
Samacsys DescriptionIC GATE NAND 4CH 2-INP 14DIP
Samacsys Manufactureronsemi
Samacsys Modified On2023-06-22 10:55:39
YTEOL0
series4000/14000/40000
JESD-30 codeR-PDIP-T14
JESD-609 codee3
length18.86 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
method of packingRAIL
Peak Reflow Temperature (Celsius)260
Prop。Delay @ Nom-Sup250 ns
propagation delay (tpd)250 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height4.69 mm
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
P SUFFIX
CASE 646
1
14
SOIC−14
D SUFFIX
CASE 751A
1
14
TSSOP−14
DT SUFFIX
CASE 948G
1
14
0xxB
ALYWG
G
140xxBG
AWLYWW
MC140xxBCP
AWLYYWWG
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
ESD Withstand Voltage
Human Body Model
Machine Model
Charged Device Model
Value
−0.5
to +18.0
−0.5
to V
DD
+ 0.5
±
10
500
−55
to +125
−65
to +150
260
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
V
ESD
Unit
V
V
mA
mW
°C
°C
°C
V
> 3000
> 300
N/A
Device
MC14001B
MC14011B
MC14023B
MC14025B
MC14071B
MC14073B
MC14081B
MC14082B
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
DEVICE INFORMATION
Description
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Triple 3−Input NAND Gate
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
Quad 2−Input AND Gate
Dual 4−Input AND Gate
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2013
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
April, 2013
Rev. 10
1
Publication Order Number:
MC14001B/D
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