Heterogeneous integration drives changes in panel process equipment (drivers). Heterogeneous integration (HI) has become the latest turning point in packaging technology.

Heterogeneous integration drives changes in panel process equipment (drivers). Heterogeneous integration (HI) has become the latest turning point in packaging technology.

Demand for system-in-package (SiP) pushes substrate design to smaller features (similar to fan-out panel-level packaging FO-PLP) 

Convergence of demand allows the R&D costs of panel-level process systems to be shared 

The continuous increase in the cost of transistor scaling has prompted the industry to find innovative ways to update and iteratively improve the performance of chips and systems. For this reason, heterogeneous integration has become the latest turning point in packaging technology. Heterogeneous integration integrates separately manufactured components into a higher-level combination that overall has greater functionality, better operating characteristics, and lower cost. This higher-level combination is called system-in-package (SiP). Heterogeneous integration was initially performed on high-performance computing devices, which are often used for machine learning and artificial intelligence applications. 

System-in-package design

Improving performance involves bringing logic and memory closer together to achieve higher-bandwidth connections than a single chip embedded on a motherboard can achieve. To increase speed and bandwidth, the industry is exploring system-in-package (SiP) designs.

System -in-package packages two or more integrated circuits together, while system-on-a-chip (SoC) integrates the functions of these chips on a single chip. 

System -in-package designs continue to evolve to include more functionality as tightly as possible. 

In some of today's most advanced devices, a single package contains dozens of chips and more than a trillion transistors. 

This diagram shows options for system-in-package design. The chart shows that to meet the demand for heterogeneous integration, new packaging technologies similar to system-in-package are needed to achieve efficient performance and accelerate time to market.

To bring logic and memory closer together, the semiconductor industry is moving system-in-package designs to integrated circuit substrates. It enables smaller features, tighter spacing, and higher input/output (I/O) volume than standard printed circuit boards. These factors result in design rules on the substrate that are more similar to those for fan-out wafer-level packaging (FO-WLP) and fan-out panel-level packaging (FO-PLP). 

Fan -out is an emerging technology that allows chips to be attached to larger-sized circular, square or rectangular substrates. Using a larger substrate size allows more chips to be accommodated in each area, thus reducing unit costs. 

 FO-PLP is packaged in a circular size of 300/330mm, which has a cost advantage compared to FOWLP. 

However, the increasing cost of developing FO-PLP technology in small batches is a huge obstacle.

R&D challenges

The primary driver of the FO-PLP market is cost (rather than performance). The challenge in this market is the need to meet wafer-level specifications and throughput at larger sizes, from 300 mm round wafers to 600 x 600 mm square panels. The market for these panels is small, resulting in insufficient levels of R&D investment across the supply chain to address the critical issues associated with processing large panels. 

Due to insufficient investment, the production level of FO-PLP is low and insufficient to obtain the economic benefits of moving to larger substrate sizes. 

As a result, most fan-out operations stop at the wafer. 

Technology integration

Similar panels (510 x 515 mm) are used in the substrate market, which is expected to see significant increases in volume over the next four years, especially in the most technically challenging areas. Since technology convergence of substrate and FO-PLP requirements (such as feature size and uniformity) is imminent, it is likely that we can address both markets using the same or similar platforms. Convergence enables a stronger equipment supplier base. By standardizing panels into several sizes and adopting existing interface and device standards, we can increase the number of common system platforms. Standardization will help reduce the research and development costs of panel-level process systems. 

Increased production will help spread costs over new equipment. This can increase scale and achieve a strong market for panel processing equipment. 

As panel production approaches wafer-level packaging levels, more applications are expected to move from wafer to panel to take advantage of expected cost advantages.

 Adjacent markets such as Micro-LED or “antenna-in-package” solutions are also expected to drive increased panel production. Higher yields will make cost reductions more likely, helping to make panel-level solutions more competitive. 

SEMSYSCO offers wet processing equipment (such as the CUPID pictured) that can handle substrates as large as 600 x 600 mm

domino effect

As production increases, it is believed that there will be a domino effect, and cost reductions will drive increased production and increased investment in R&D. These investments will help drive more effective automation, more machine learning and intelligence, greater reliability and fewer defects. All of this will lead to cost reductions, which will continue to drive increased panel business volume.

Lam Group has been committed to promoting innovation in the semiconductor industry. Through our previous acquisition of SEMSYSCO we are investing in the panel-level process market and are at the forefront of innovation.