CD74HCT107 datasheet, PDF - EEWORLD Datasheet

CD74HCT107: DescriptionCD74HCT107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset; Categorysemiconductor logic; File Size972KB，18 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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CD74HCT107 Overview

CD74HCT107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

	CD74HCT107	5962-8515401CA	CD54HC107F3A	CD54HC107	CD74HC107
Description	CD74HCT107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset	High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125	High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125	CD54HC107 High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset	CD74HC107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
Schmitt trigger	No	No	No	No	No
tpd @ nom Voltage(Max)(ns)	43	-	-	51	51
Rating	Catalog	-	-	Military	Catalog
IOL(Max)(mA)	6	-	-	-6	6
Voltage(Nom)(V)	5	-	-	3.3,5	3.3,5
IOH(Max)(mA)	-6	-	-	6	-6
ICC @ nom voltage(Max)(mA)	0.04	-	-	0.04	0.04
F @ nom voltage(Max)(Mhz)	25	-	-	70	70
Package Group	PDIP\|14	-	-	CDIP\|14	PDIP\|14,SOIC\|14
VCC(Max)(V)	5.5	-	-	6	6
Technology Family	HCT	-	-	HC	HC
VCC(Min)(V)	4.5	-	-	2	2
Bits(#)	2	-	-	2	2

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