IW4034B
8-S
TAGE
S
TATIC
B
IDIRECTIONAL
P
ARALLEL
/
S
ERIAL
I
NPUT
/O
UTPUT
B
US
R
EGISTER
High-Voltage Silicon-Gate CMOS
The IW4034B is a static eight-stage parallel-or serial-input
parallel-output register. It can be used to:
1) bidirectionally transfer parallel information between two
buses, 2) convert serial data to parallel form and direct the
parallel data to either of two buses, 3) store (recirculate) parallel
data, or 4) accept parallel data from either of two buses and
convert that data to serial form. Inputs that control the operations
include a single-phase CLOCK (CL), A DATA ENABLE (AE),
ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/
B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S).
ORDERING INFORMATION
Data inputs include 16 bidirectional parallel data lines of which
IW4034BN Plastic
the eight A data lines are inputs (3-state outputs) and the B data
IW4034BDW SOIC
lines are outputs (inputs) dependung on the signal level on the
T
A
= -55° to 125° C for all
A/B input. In addition, an input for SERIAL DATA is also
packages
provided.
All register stages are D-type master-slave flip-flops with separate master and slave clock inputs
generated internally to allow synchronous or asynchronous data transfer from master to slave.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-temperature range; 100 nA at 18 V
and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=V
CC
PIN 12= GND
1
IW4034B
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +20
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
mA
±10
P
D
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
P
D
r Dissipation per Output Transistor
100
mW
Tstg
Storage Temperature
-65 to +150
°C
260
T
L
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
V
CC
DC Supply Voltage (Referenced to GND)
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to
GND)
T
A
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, V
IN
and
V
OUT
should be constrained to the range GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
V
CC
). Unused outputs must be left open.
2
IW4034B
DC ELECTRICAL CHARACTERISTICS(Voltages
Referenced to GND)
Guaranteed Limit
V
CC
Symbol
Parameter
Test Conditions
V
≥-55°C
25°C
≤125
Unit
°C
V
3.5
3.5
3.5
V
IH
Minimum
High-
V
OUT
= 0.5 V or V
CC
- 0.5V
5.0
V
OUT
= 1.0 V or V
CC
- 1.0 V
10
7
7
7
Level
Input
V
OUT
= 1.5 V V
CC
- 1.5V
11
11
11
Voltage
15
V
1.5
1.5
1.5
V
IL
Maximum Low -
V
OUT
= 0.5 V or V
CC
- 0.5V
5.0
3
3
3
Level
Input
V
OUT
= 1.0 V or V
CC
- 1.0 V
10
V
OUT
= 1.5 V V
CC
- 1.5V
4
4
4
Voltage
15
V
4.95
4.95
4.95
V
OH
Minimum
High- V
IN
=GND or V
CC
5.0
9.95
9.95
9.95
Level
Output
10
Voltage
15 14.95 14.95 14.95
V
0.05
0.05
0.05
V
OL
Maximum
Low- V
IN
=GND or V
CC
5.0
0.05
0.05
0.05
Level
Output
10
0.05
0.05
0.05
Voltage
15
I
IN
Maximum
Input V
IN
= GND or V
CC
18
±0.1
±0.1
±1.0 µA
Leakage Current
in
High- 18
I
OZ
Minimum
Three Output
±0.4
±0.4 ±12.0 µA
State
State
Leakage Impedance
V
IN
= GND or V
CC
Current
V
OUT
= GND or V
CC
150
5
V
IN
= GND or V
CC
5
I
CC
Maximum
5.0
µA
300
10
10
Quiescent Supply
10
600
20
20
Current
15
3000
100
100
(per Package)
20
mA
I
OL
Minimum Output V
IN
= GND or V
CC
0.36
0.51
0.64
Low
(Sink) U
OL
=0.4 V
5.0
0.9
1.3
1.6
Current
10
U
OL
=0.5 V
2.4
3.4
4.2
15
U
OL
=1.5 V
mA
I
OH
Minimum Output V
IN
= GND or V
CC
-1.6 -1.15
-2
5.0
High
(Source) U
OH
=2.5 V
5.0 -0.64 -0.51 -0.36
Current
U
OH
=4.6 V
-0.9
-1.3
-1.6
10
U
OH
=9.5 V
-2.4
-3.4
-4.2
15
U
OH
=13.5 V
3
IW4034B
AC ELECTRICAL CHARACTERISTICS(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
Symbol
f
max
t
PHL
,
t
PLH
Parameter
Maximum Clock Frequency (Figure 2)
Maximum Propagation Delay, A(B)
Parallel Data In to B(A) Parallel Data
Out; Serial to Parallel Data Out (Figures
1,2)
Maximum Propagation Delay, A/B or
AE to “A” Output (Figure 3)
V
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
-
Guaranteed Limit
≥-55
25°C
≤125
°C
°C
1
2
2
2.5
5
5
3.5
7
7
1400
700
700
480
240
240
340
170
170
400
160
120
200
100
80
400
160
120
200
100
80
7.5
800
320
240
400
200
160
Unit
MHz
ns
t
PLZ
,
t
PHZ,
t
PZL
,
t
PZH
t
THL
, t
TLH
Maximum Output Transition Time, Any
Output (Figures 1,2)
C
IN
Maximum Input Capacitance
ns
ns
pF
TIMING REQUIREMENTS(C
L
=50pF, R
L
=200 kΩ, Input t
r
=t
f
=20 ns)
Guaranteed Limit
V
CC
Symbol
Parameter
V
≥-
25°C
≤125°
C
55°C
320
160
160
t
su
Minimum Setup Time, Serial Data to 5.0
120
60
60
Clock (Figure 4)
10
80
40
40
15
100
50
50
t
su
Minimum Setup Time, Parallel Data to 5.0
60
30
30
Clock (Figure 4)
10
40
20
20
15
100
50
50
t
h
Minimum Hold Time, Clock to Data 5.0
30
15
15
(Figure 4)
10
20
10
10
15
700
350
350
t
w
Minimum Pulse Width, AE, P/S, A/S 5.0
280
140
140
(Figure 5)
10
160
80
80
15
500
250
250
t
w
Minimum Pulse Width, Clock (Figure 2) 5.0
200
100
100
10
140
70
70
15
30
15
15
t
r
,t
f
Minimum Input Rise or Fall Time, Clock 5.0
30
15
15
(Figure 2)
10
30
15
15
15
Unit
ns
ns
ns
ns
ns
ns
4
IW4034B
TRUTH TABLE FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION
“A”
Enable P/S A/B A/S
Operation
*
L
L
L
X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs
Disabled
L
L
H
X Serial Mode, Synch. Serial Data Input, “B” Parallel Data Output
L
H
L
L Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data
Outputs Disabled
L
H
L
H Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data
Outputs Disabled
L
H
H
L Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data
Outputs, Synch. Data Recirculation
L
H
H
H Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data
Outputs, Asynch. Data Recirculation
H
L
L
X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output
H
L
H
X Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
H
H
L
L Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data
Output
H
H
L
H Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data
Output
H
H
H
L Parallel Mode; “A” Synch. Parallel Data Input, “B” Parallel Data
Output
H
H
H
H Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data
Output
*
Outputs change at positive transition of clock in the serial mode and when the A/S control
input is “low” in the parallel mode. During transfer from parallel to serial operation A/S should
remain low in oder to prevent D
S
transfer into Flip Flops.
X = Don’t Care
PARALLEL OPERATION
A high P/S input signal allows data transfer into the register via the parallel data lines
synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input
is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B
input. When this signal is high the A data lines are inputs (and B data lines are outputs); a low A/B
signal reverses the direction of data flow.
The AE input is an additional feature which allows many registers to feed data to a common
bus. The A DATA lines are enabled only when this signal is high.
Data storage through recirculation of data in each register stage is accomplished by making
the A/B signal high and the AE signal low.
SERIAL OPERATION
A low P/S signal allows serial data to transfer into the register synchronously with the positive
transition of the clock. The A/S input is internally disabled when the register is in the serial mode
(asynchronous serial operation is not allowed).
The serial data appears as output data on either the B lines (when A/B is high) or the A lines
(when A/B is low and the AE signal is high).
5
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