QL3040-1PQ240I datasheet, PDF - EEWORLD Datasheet

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QL3040-1PQ240I: DescriptionField Programmable Gate Array, 1008 CLBs, 40000 Gates, 250MHz, 1008-Cell, CMOS, PQFP240, PLASTIC, QFP-240; CategoryProgrammable logic devices Programmable logic; File Size187KB，11 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL3040-1PQ240I Overview

Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 250MHz, 1008-Cell, CMOS, PQFP240, PLASTIC, QFP-240

QL3040-1PQ240I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	QFP
package instruction	QFP, QFP240,1.3SQ,20
Contacts	240
Reach Compliance Code	compliant
maximum clock frequency	250 MHz
Combined latency of CLB-Max	3.5 ns
JESD-30 code	S-PQFP-G240
JESD-609 code	e0
Humidity sensitivity level	3
Configurable number of logic blocks	1008
Equivalent number of gates	40000
Number of entries	202
Number of logical units	1008
Output times	194
Number of terminals	240
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1008 CLBS, 40000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP240,1.3SQ,20
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3,3.3/5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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QL3040 / QL3040R

40,000 Usable PLD Gate pASIC

3 FPGA

Combining High Performance

and

High Density

PRELIMINARY DATA

pASIC 3

HIGHLIGHTS

March, 1998

High Performance and High Density

-40,000 Usable PLD Gates with 252 I/Os

-16-bit counter speeds over 250 MHz, data path speeds over 275 MHz

-0.35µm four-layer metal non-volatile CMOS process for smallest die sizes

pASIC 3

… 40,000

usable PLD gates,

252 I/O pins

Easy to Use / Fast Development Cycles

-100% routable with 100% utilization and complete pin-out stability

-Variable-grain logic cells provide high performance and 100% utilization

-Comprehensive design tools include high quality Verilog/VHDL synthesis

20,736 bit RAM

Option

High Speed Embedded SRAM Available in “R” Versions

-18 dual-port RAM modules, organized in user-configurable 1,152-bit blocks

-5ns access times, each port independently accessible

-Fast and efficient for FIFO, RAM, and ROM functions

Advanced I/O Capabilities

-Interfaces with both 3.3 volt and 5.0 volt devices

-PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades

-Full JTAG boundary scan

-Registered I/O cells with individually controlled clocks and output enables

QL3040

Block Diagram

1,008

Logic

Cells

2-37

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