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IDT71V424L10PHI

Description
512K X 8 STANDARD SRAM, 15 ns, PDSO36
Categorystorage   
File Size73KB,9 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT71V424L10PHI Overview

512K X 8 STANDARD SRAM, 15 ns, PDSO36

IDT71V424L10PHI Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals36
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage3 V
Rated supply voltage3.3 V
maximum access time15 ns
Processing package description0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-36
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE
surface mountYes
Terminal formJ BEND
Terminal spacing1.27 mm
terminal coatingMATTE TIN
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelCOMMERCIAL
memory width8
organize512K X 8
storage density4.19E6 deg
operating modeASYNCHRONOUS
Number of digits524288 words
Number of digits512K
Memory IC typeSTANDARD SRAM
serial parallelPARALLEL
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
Features
IDT71V424S
IDT71V424L
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Functional Block Diagram
A
0
A
18
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O
0
- I/O
7
8
I/O CONTROL
8
8
WE
OE
CS
CONTROL
LOGIC
3622 drw 01
JULY 2004
1
©2004 Integrated Device Technology, Inc.
DSC-3622/06
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