EEWORLDEEWORLDEEWORLD

Part Number

Search

70V24L55GG8

Description
Dual-Port SRAM
Categorystorage    storage   
File Size725KB,26 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

70V24L55GG8 Overview

Dual-Port SRAM

70V24L55GG8 Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
package instructionPGA,
Reach Compliance Codecompliant
Maximum access time55 ns
JESD-30 codeS-CPGA-P84
memory density65536 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Number of functions1
Number of terminals84
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4KX16
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formPIN/PEG
Terminal locationPERPENDICULAR
Base Number Matches1
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
IDT70V35/34S/L
IDT70V25/24S/L
Features
Functional Block Diagram
R/W
L
UB
L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70V35/34
– Commercial: 15/20/25ns (max.)
– Industrial: 20ns
IDT70V25
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns
IDT70V24
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20ns
Low-power operation
– IDT70V35/34S
– IDT70V35/34L
Active: 430mW (typ.)
Active: 415mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660
µ
W (typ.)
– IDT70V25/24S
– IDT70V25/24L
Active: 400mW (typ.)
Active: 380mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
Control
I/O
0L
-I/O
8L
(4)
BUSY
L
A
12L
(1)
A
0L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
A
12R
(1)
A
0R
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
SEM
L
INT
L
(3)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5624 drw 01
NOTES:
1. A
12
is a NC for IDT70V34 and for IDT70V24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70V25/24.
5. I/O
8
x - I/O
15
x for IDT70V25/24.
©2015 Integrated Device Technology, Inc.
M/S
AUGUST 2015
1
DSC-5624/8

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号