Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FEATURES
•
Wide supply voltage range from 1.65 to 5.5 V
•
High noise immunity
•
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
• ±24
mA output drive (V
CC
= 3.0 V)
•
CMOS low power consumption
•
Latch-up performance
≤250
mA
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5 V
•
SOT353 package.
DESCRIPTION
74LVC1G79
The 74LVC1G79 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of this device in a mixed 3.3 and 5 V
environment.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G79 provides a single positive-edge triggered
D-type flip-flop.
Information on the data input is transferred to the Q output
on the LOW-to-HIGH transition of the clock pulse.
The D input must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay CP to Q
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
input capacitance
power dissipation capacitance per
buffer
V
CC
= 3.3 V; note 1
TYPICAL
3.6
2.3
2.2
1.7
5
17
ns
ns
ns
ns
pF
pF
UNIT
2001 Apr 04
2
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FUNCTION TABLE
See note 1.
INPUT
CP
↑
↑
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH CP transition;
X = don’t care;
D
L
H
X
74LVC1G79
OUTPUT
Q
L
H
q
q = lower case indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74LVC1G79GW
PINNING
PIN
1
2
3
4
5
D
CP
GND
Q
V
CC
SYMBOL
data input D
clock pulse input CP
ground (0 V)
data output Q
supply voltage
DESCRIPTION
TEMPERATURE
RANGE
−40
to +85
°C
PINS
5
PACKAGE
SC-88A
MATERIAL
plastic
CODE
SOT353
MARKING
VP
2001 Apr 04
3
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
operating ambient temperature
input rise and fall times
V
CC
= 1.65 to 2.7 V
V
CC
= 2.7 to 5.5 V
active mode
Power-down mode; V
CC
= 0 V
CONDITIONS
0
0
0
−40
0
0
MIN.
1.65
74LVC1G79
MAX.
5.5
5.5
V
CC
5.5
+85
20
10
V
V
V
V
°C
UNIT
ns/V
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
V
I
< 0
note 1
V
O
> V
CC
or V
O
< 0
active mode; notes 1 and 2
Power-down mode;
notes 1 and 2
I
O
I
CC
, I
GND
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V
CC
is powered-down to 0 V, the output voltage can be 5.5 V in normal operation.
3. Above 55
°C
the value of P
D
derates linearly with 2.5 mW/K.
output source or sink current
V
CC
or GND current
storage temperature
power dissipation per package
for temperature range from
−40
to +85
°C;
note 3
V
O
= 0 to V
CC
CONDITIONS
−
−0.5
−
−0.5
−0.5
−
−
−65
−
MIN.
−0.5
MAX.
+6.5
−50
+6.5
±50
V
CC
+ 0.5
+6.5
±50
±100
+150
200
V
mA
V
mA
V
V
mA
mA
°C
mW
UNIT
2001 Apr 04
5