Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
F
EATURES
•
1:1 Differential LVPECL-to-LVPECL / ECL buffer
•
1 LVPECL clock output pair
•
1 Differential LVPECL PCLK, nPCLK input pair
•
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
•
Maximum output frequency: >2.5GHz
•
Part-to-part skew: 100ps (maximum)
•
Propagation delay: 500ps (maximum)
•
Additive phase jitter, RMS: 0.03ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 5.25V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -5.25V to -2.375V
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS853001 is a 1:1 Differential LVPECL-
to-LVPE C L B u f fe r a n d a m e m b e r o f t h e
HiPerClockS™
HiPerClock S ™ family of High Perfor mance
Clock Solutions from ICS. The ICS853001
may be used to regenerate LVPECL clocks which
may have been attenuated, across a long trace, or may also
be used as a differential-to-LVPECL translator. The differen-
tial input can accept the following differential input types:
LVPECL, LVDS and CML. The device also has an output en-
able pin for debug/test purposes. When the output is disabled,
it drives differential LOW (Q = LOW, nQ = HIGH). The
ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP
or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on
space-constrained boards.
ICS
B
LOCK
D
IAGRAM
OE
P
IN
A
SSIGNMENT
D Q
V
CC
Q
nQ
V
EE
Q
1
2
3
4
8
7
6
5
OE
PCLK
nPCLK
V
BB
LE
PCLK
nQ
nPCLK
ICS853001
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
V
BB
ICS853001
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
853001AG
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 29, 2005
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
Type
Power
Output
Power
Output
Description
Positive supply pin.
Differential output pair. LVPECL interface levels.
Negative supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6
7
8
NOTE:
Name
V
CC
Q, nQ
V
EE
V
BB
Nominal bias voltage at V
CC
- 1.38V.
Pullup/ Inver ting differential LVPECL clock input. V
CC
/2 default when left
nPCLK
Input
Pulldown floating. Can accept LVPECL, LVDS, CML interface levels.
Non-inver ting differential LVPECL clock input.
PCLK
Input
Pulldown
Can accept LVPECL, LVDS, CML interface levels.
Active HIGH output enable. When logic HIGH, the output is enabled
and follows the input clock. When logic LOW, the output drives logic
OE
Input
Pullup
low (Q=LOW, nQ=HIGH). LVCMOS/LVTTL interface levels.
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
PULLUP
Parameter
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
37.5
37.5
Maximum
Units
KΩ
KΩ
853001AG
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 29, 2005
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
6V (LVPECL mode, V
EE
= 0)
-6V (ECL mode, V
CC
= 0)
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
50mA
100mA
± 0.5mA
-65°C to 150°C
101.7°C/W (0 m/s)
112.7°C/W (0 lfpm)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
8 Lead TSSOP
8 Lead SOIC
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
5.25V; V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
5.25
27
Units
V
mA
T
ABLE
3B. LVCMOS DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
5.25V; V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
OE
OE
V
CC
= V
IN
V
CC
= V
IN
-150
Test Conditions
Minimum
0.7V
CC
-0.3
Typical
Maximum
V
CC
+ 0.3
0.3V
CC
150
Units
V
V
µA
µA
T
ABLE
3C. LVCMOS DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.25V
TO
-2.375V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
OE
OE
V
CC
= V
IN
V
CC
= V
IN
-150
Test Conditions
Minimum
0.3V
EE
V
EE
- 0.3
Typical
Maximum
0.3
0.7V
EE
150
Units
V
V
µA
µA
853001AG
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 29, 2005
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
Test Conditions
PCLK
nPCLK
PCLK
nPCLK
V
CC
= V
IN
V
CC
= V
IN
V
CC
= 5.25, V
IN
= 0V
V
CC
= 5.25V, V
IN
= 0V
-200
-200
0.15
1.2
V
CC
- 1.005
V
CC
- 1.78
0.6
1.0
V
CC
- 1.32
1.2
V
CC
Minimum
Typical
Maximum
200
200
Units
µA
µA
µA
µA
V
V
V
V
V
V
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
5.25V; V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High Current
Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak Output Voltage Swing
Bias Voltage
V
CC
- 1.44 V
CC
- 1.38
V
BB
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.25V
TO
-2.375V
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
IJ 1GHz
OR
V
CC
= 2.375
TO
5.25V; V
EE
= 0V, T
A
= -40°C
TO
85°C
Test Conditions
Minimum
250
Typical
Maximum
>2.5
500
100
Units
GHz
ps
ps
ps
t
sk(pp)
t
jit
t
R
/ t
F
odc
155.52MHz, Integration Range:
12KHz - 20MHz
20% to 80%
V
CC
= 2.375V to 3.6V, V
EE
= 0
0.03
50
48
250
52
54
ps
%
%
V
CC
> 3.6V to 5.25V, V
EE
= 0 or
46
V
EE
= -5.25V to -3.6V,V
CC
= 0
All parameters are measured at ƒ
≤
1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
853001AG
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 29, 2005
Integrated
Circuit
Systems, Inc.
ICS853001
1:1, D
IFFERENTIAL
LVPECL-
TO
-
2.5V, 3.3V, 5V LVPECL/ECL B
UFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
-60
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz)
= 0.03ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
853001AG
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 29, 2005
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