HB52RD328DC-F
256 MB Unbuffered SDRAM S.O.DIMM
32-Mword
×
64-bit, 100 MHz Memory Bus, 2-Bank Module
(32 pcs of 16 M
×
4 components)
PC100 SDRAM
ADE-203-1044B (Z)
Rev. 1.0
Jan. 18, 2000
Description
The HB52RD328DC is a 16M
×
64
×
2 banks Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 32 pieces of 64-Mbit SDRAM (HM5264405FTB) sealed in TCP
package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the
product is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density
mounting possible without surface mount technology. It provides common data inputs and outputs.
Decoupling capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
•
Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM
•
144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 67.60 mm (Length)
×
31.75 mm (Height)
×
3.80 mm (Thickness)
Lead pitch: 0.80 mm
•
3.3 V power supply
•
Clock frequency: 100 MHz (max)
•
LVTTL interface
•
Data bus width:
×
64 Non parity
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length : 1/2/4/8/full page
HB52RD328DC-F
•
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
interleave (BL = 1/2/4/8)
•
Programmable
CE
latency
•
Byte control by DQMB
•
Refresh cycles: 4096 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Low self refresh current: HB52RD328DC-A6FL/B6FL (L-version)
•
Full page burst length capability
Sequential burst
Burst stop capability
: 2/3 (HB52RD328DC-A6F/A6FL)
: 3 (HB52RD328DC-B6F/B6FL)
Ordering Information
Type No.
HB52RD328DC-A6F
HB52RD328DC-B6F
HB52RD328DC-A6FL
HB52RD328DC-B6FL
Frequency
100 MHz
100 MHz
100 MHz
100 MHz
CE
latency
2/3
3
2/3
3
Package
Small outline DIMM (144-pin)
Contact pad
Gold
2
HB52RD328DC-F
Pin Description
Pin name
A0 to A11
Function
Address input
Row address
Column address
A12/A13
DQ0 to DQ63
S0/S1
RE
CE
W
DQMB0 to DQMB7
CK0/CK1
CKE0/CKE1
SDA
SCL
V
CC
V
SS
NC
Bank select address
Data-input/output
Chip select
Row address asserted bank enable
Column address asserted
Write enable
Byte input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
Ground
No connection
A0 to A11
A0 to A9
BA1, BA0
5