HEF4015BTD-T datasheet, PDF - EEWORLD Datasheet

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HEF4015BTD-T: DescriptionIC 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Shift Register; Categorylogic logic; File Size71KB，14 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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HEF4015BTD-T Overview

IC 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Shift Register

HEF4015BTD-T Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	unknown
Other features	INDIVIDUAL CLOCK & CLEAR FOR EACH SHIFT REGISTER
Counting direction	RIGHT
series	4000/14000/40000
JESD-30 code	R-PDSO-G16
length	9.9 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	SERIAL IN PARALLEL OUT
Humidity sensitivity level	1
Number of digits	4
Number of functions	2
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	260 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	15 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
Trigger type	POSITIVE EDGE
width	3.9 mm
minfmax	7 MHz
Base Number Matches	1

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HEF4015B

Dual 4-bit static shift register

Rev. 06 — 3 November 2009

Product data sheet

1. General description

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel

converter). Each shift register has a serial data input (D), a clock input (CP), four fully

buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input

(MR). Information present on D is shifted to the ﬁrst register position, and all the data in

the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A

HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.

The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise

and fall times.

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input. It is

also suitable for use over the full industrial (−40

°C

to +85

°C)

temperature range.

2. Features

Tolerant of slow clock rise and fall times

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the automotive temperature range

−40 °C

to +85

°C.

Complies with JEDEC standard JESD 13-B

3. Applications

Serial-to-parallel converter

Buffer stores

General purpose register

4. Ordering information

Table 1.

Ordering information

All types operate from

−

C to +85

Type number

HEF4015BP

HEF4015BT

Package

Name

DIP16

SO16

Description

plastic dual in-line package; 16 leads (300 mil)

plastic small outline package; 16 leads; body width 3.9 mm

Version

SOT38-4

SOT109-1

HEF4015BTD-T Related Products

	HEF4015BTD-T	HEF4015BPN
Description	IC 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Shift Register	IC 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16, Shift Register
Source Url Status Check Date	2013-06-14 00:00:00	2013-06-14 00:00:00
Is it Rohs certified?	conform to	conform to
Parts packaging code	SOIC	DIP
package instruction	SOP,	DIP,
Contacts	16	16
Reach Compliance Code	unknown	compliant
Other features	INDIVIDUAL CLOCK & CLEAR FOR EACH SHIFT REGISTER	INDIVIDUAL CLOCK & CLEAR FOR EACH SHIFT REGISTER
Counting direction	RIGHT	RIGHT
series	4000/14000/40000	4000/14000/40000
JESD-30 code	R-PDSO-G16	R-PDIP-T16
length	9.9 mm	21.6 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	SERIAL IN PARALLEL OUT	SERIAL IN PARALLEL OUT
Number of digits	4	4
Number of functions	2	2
Number of terminals	16	16
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	DIP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	IN-LINE
Peak Reflow Temperature (Celsius)	260	245
propagation delay (tpd)	260 ns	260 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	4.7 mm
Maximum supply voltage (Vsup)	15 V	15 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	NO
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	40	40
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	3.9 mm	7.62 mm
minfmax	7 MHz	7 MHz
Base Number Matches	1	1

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