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QL3060-1PQ240I

Description
Field Programmable Gate Array, 1584 CLBs, 60000 Gates, 250MHz, 1584-Cell, CMOS, PQFP240, PLASTIC, QFP-240
CategoryProgrammable logic devices    Programmable logic   
File Size197KB,11 Pages
ManufacturerQuickLogic Corporation
Websitehttps://www.quicklogic.com
Download Datasheet Parametric View All

QL3060-1PQ240I Overview

Field Programmable Gate Array, 1584 CLBs, 60000 Gates, 250MHz, 1584-Cell, CMOS, PQFP240, PLASTIC, QFP-240

QL3060-1PQ240I Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerQuickLogic Corporation
Parts packaging codeQFP
package instructionQFP, QFP240,1.3SQ,20
Contacts240
Reach Compliance Codecompliant
maximum clock frequency250 MHz
Combined latency of CLB-Max3.5 ns
JESD-30 codeS-PQFP-G240
JESD-609 codee0
Humidity sensitivity level3
Configurable number of logic blocks1584
Equivalent number of gates60000
Number of entries202
Number of logical units1584
Output times194
Number of terminals240
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize1584 CLBS, 60000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP240,1.3SQ,20
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3,3.3/5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
QL3060 / QL3060R
60,000 Usable PLD Gate pASIC
®
3 FPGA
Combining High Performance
and
High Density
PRELIMINARY DATA
pASIC 3
HIGHLIGHTS
March, 1998
2
High Performance and High Density
-60,000 Usable PLD Gates with 316 I/Os
-16-bit counter speeds over 250 MHz, data path speeds over 275 MHz
-0.35µm four-layer metal non-volatile CMOS process for smallest die sizes
pASIC 3
… 60,000
usable PLD gates,
316 I/O pins
Easy to Use / Fast Development Cycles
-100% routable with 100% utilization and complete pin-out stability
-Variable-grain logic cells provide high performance and 100% utilization
-Comprehensive design tools include high quality Verilog/VHDL synthesis
High Speed Embedded SRAM Available in “R” Versions
-22 dual-port RAM modules, organized in user-configurable 1,152-bit blocks
-5ns access times, each port independently accessible
-Fast and efficient for FIFO, RAM, and ROM functions
Advanced I/O Capabilities
-Interfaces with both 3.3 volt and 5.0 volt devices
-PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades
-Full JTAG boundary scan
-Registered I/O cells with individually controlled clocks and output enables
QL3060
Block Diagram
1,584
Logic
Cells
2-47

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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