M24256-BRDW6 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> storage> M24256-BRDW6

M24256-BRDW6: Description32K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8; Categorystorage storage; File Size729KB，46 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

Download Datasheet Parametric View All

M24256-BRDW6 Overview

32K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8

M24256-BRDW6 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	0.169 INCH, TSSOP-8
Contacts	8
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum clock frequency (fCLK)	0.4 MHz
Data retention time - minimum	40
Durability	100000 Write/Erase Cycles
I2C control byte	1010DDDR
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.4 mm
memory density	262144 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	8
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP8,.16
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2/3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Serial bus type	I2C
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.8 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm
Maximum write cycle time (tWC)	10 ms
write protect	HARDWARE

Preview

Download Datasheet

View All

M24128-BW M24128-BR

M24128-BF M24128-DF

128-Kbit serial I²C bus EEPROM

Datasheet

production data

Features

•

Compatible with all I

C bus modes:

– 1 MHz

– 400 kHz

– 100 kHz

TSSOP8 (DW)

169 mil width

•

Memory array:

– 128 Kbit (16 Kbyte) of EEPROM

– Page size: 64 byte

– Additional Write lockable page (M24128-D

order codes)

•

Single supply voltage and high speed:

– 1 MHz clock from 1.7 V to 5.5 V

SO8 (MN)

150 mil width

•

Write:

– Byte Write within 5 ms

– Page Write within 5 ms

•

Operating temperature range:

– from -40 °C up to +85 °C

•

Random and sequential Read modes

•

Write protect of the whole memory array

UFDFPN8 (MC)

DFN8 - 2x3 mm

•

Enhanced ESD/Latch-Up protection

•

More than 4 million Write cycles

•

More than 200-years data retention

Packages

WLCSP (CS)

UFDFPN5 (MH)

DFN5 - 1.7x1.4 mm

•

SO8 ECOPACK2

•

TSSOP8 ECOPACK2

•

UFDFPN8 ECOPACK2

•

WLCSP ECOPACK2

•

UFDFPN5 ECOPACK2

•

Unsawn wafer (each die is tested)

Unsawn wafer

September 2017

This is information on a product in full production.

DocID16892 Rev 30

1/46

www.st.com

Contents

M24128-BW M24128-BR M24128-BF M24128-DF

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

2.5

2.6

Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

(ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Supply voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6.1

2.6.2

2.6.3

2.6.4

Operating supply voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

4.2

4.3

4.4

4.5

Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1

Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write Identification Page (M24128-D only) . . . . . . . . . . . . . . . . . . . . . . 17

Lock Identification Page (M24128-D only) . . . . . . . . . . . . . . . . . . . . . . . 17

ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17

Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18

Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2

Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.1

2/46

DocID16892 Rev 30

List of tables

M24128-BW M24128-BR M24128-BF M24128-DF

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DC characteristics (M24128-BW, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DC characteristics (M24128-BR device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC characteristics (M24128-BF, M24128-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . 28

400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch

dual flat package, no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package,

no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

WLCSP - 8-bump, 1.289 x 1.099 mm, 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4/46

DocID16892 Rev 30

M24128-BW M24128-BR M24128-BF M24128-DF

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

UFDFPN5 (DFN5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

WLCSP connections for the M24128-DFCS6TP/K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16

Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Maximum Rbus value versus bus parasitic capacitance (Cbus) for

an I2C bus at maximum frequency fC = 400 kHz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Maximum R

bus

value versus bus parasitic capacitance C

bus

) for

an I

C bus at maximum frequency f

= 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

UFDFPN5 – 1.7x1.4 mm, 0.55 mm thickness, ultra thin fine pitch

dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch

dual flat package, no lead recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch

dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline,

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline . 37

SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width,

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

WLCSP - 8-bump, 1.289 x 1.099 mm, 0.4 mm pitch wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

WLCSP - 8-bump, 1.289 x 1.099 mm, 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DocID16892 Rev 30

5/46

Recommended Resources

Ace op amp direct push bile duct power amplifier

Practical automatic circuit thermometer

PFC boost converter circuit diagram using TOP switch

sample/hold circuit

Payphone charge meter

Multifunctional high-precision ramp oscillator

AD PCB ad cannot be selected after copper coating, it is not a problem of which layer: I can't select the copper part after the ad is covered. I created it on the top layer and immediately selected it. I tried it on other layers, but they can't be selected after they are created. I can ...; 示范法 PCB Design

About fatalerror in Modelsim simulation: ISE feels pretty good. Modelsim just prompts this. Is there any brother who can teach me?...; li617296559 FPGA/CPLD

Several concepts about switching power supply: [i=s] This post was last edited by qwqwqw2088 on 2019-2-27 08:52 [/i] [b][size=4]Ripple[/size][/b] [size=4]The output of a switching power supply is not truly constant. There is periodic jitter in the...; qwqwqw2088 Analogue and Mixed Signal

Review summary: Shanghai Hangxin ACM32F070 development board + touch function evaluation board: Activity details: [Shanghai Hangxin ACM32F070 development board + touch function evaluation board]Updated to 2022-11-09Evaluation report summary:@mars4zhu[Shanghai Hangxin ACM32F070 development board ...; EEWORLD社区 Special Edition for Assessment Centres

Register Control of LMX2592: I use TI's LMX2592 chip to generate a 5G clock signal, and use FPGA to control its registers using the SPI method. The hardware is designed by myself, and the power supply of the chip is measured to b...; yangyang_l TI Technology Forum

[Fudan Micro FM33LG0 Series Development Board Review] LCD Usage and Truth Table Tool Instructions: [i=s]This post was last edited by AE007 on 2021-11-29 02:04[/i]This test is of FM33LG0 LCD module, and LCD truth table tool can be used to quickly define the display data register data corresponding t...; AE007 Domestic Chip Exchange

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components