DS1004Z-5/T&R datasheet, PDF - EEWORLD Datasheet

DS1004Z-5/T&R: DescriptionSilicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, SOIC-8; Categorylogic logic; File Size54KB，6 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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DS1004Z-5/T&R Overview

Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, SOIC-8

Parameter Name	Attribute value
Maker	DALLAS
package instruction	0.150 INCH, SOIC-8
Reach Compliance Code	unknown
Other features	INPUT TO 1ST TAP DELAY = 5NS
series	CMOS/TTL
Input frequency maximum value (fmax)	25 MHz
JESD-30 code	R-PDSO-G8
Load capacitance (CL)	15 pF
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
programmable delay line	NO
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal location	DUAL
Total delay nominal (td)	25 ns
Base Number Matches	1

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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