Revision 1
Military Grade SmartFusion Customizable System-on-Chip (cSoC)
Product Benefits
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100% Military Temperature Tested and Qualified from
–55°C to 125°C
Not Susceptible to Neutron-Induced Configuration Loss
Hard 50 MHz 32-Bit ARM
®
Cortex™-M3
– Fully Tested Across Military Temperature Range
(–55°C to 125°C)
– 1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
– Memory Protection Unit (MPU)
– Single Cycle Multiplication, Hardware Divide
– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory
Bandwidth,
1
Allowing Multi-Master Schemes
10/100 Ethernet MAC with RMII Interface
2
Programmable External Memory Controller, Which
Supports:
– Asynchronous Memories
– NOR Flash, SRAM, PSRAM
– Synchronous SRAMs
Two I
2
C Peripherals
Two 16550 Compatible UARTs
Two SPI Peripherals
Two 32-Bit Timers
32-Bit Watchdog Timer
8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
Clock Sources
– 32 KHz to 20 MHz Main Oscillator
– Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
– 100 MHz Embedded RC Oscillator; Up to 3%
Accurate at Military Temperature
– Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)
Based on proven ProASIC
®
3 FPGA Fabric
Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
Nonvolatile, Live at Power-Up, Retains Program When
Powered Off
350 MHz System Performance
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Embedded SRAMs and FIFOs
– Variable Aspect Ratio 4,608-Bit SRAM Blocks
– x1, x2, x4, x9, and x18 Organizations
– True Dual-Port SRAM (excluding x18)
– Programmable Embedded FIFO Control Logic
Secure ISP with 128-Bit AES via JTAG
FlashLock
®
to Secure FPGA Contents
Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75 to
350 MHz
Microcontroller Subsystem (MSS)
Programmable Analog
Analog Front-End (AFE)
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Up to Three 12-Bit SAR ADCs
– 500 Ksps in 12-Bit Mode
– 550 Ksps in 10-Bit Mode
– 600 Ksps in 8-Bit Mode
Internal 2.56 V Reference or Optional External
Reference
One First-Order
ΣΔ
DAC (sigma-delta) per ADC
– 12-Bit 500 Ksps Update Rate
Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
– Two High-Voltage Bipolar Voltage Monitors (with 4
input ranges from ±2.5 V to –11.5/12 V) with 4%
Accuracy
– High Gain Current Monitor, Differential Gain = 50, up
to 12 V Common Mode
– Temperature Monitor (Resolution = ¼°C in 12-Bit
Mode; Accurate from –55°C to 150°C)
Up to Ten High-Speed Voltage Comparators
(t
pd
= 15 ns)
Offloads Cortex-M3–Based MSS from Analog
Initialization and Processing of ADC, DAC, and SCBs
Sample Sequence Engine for ADC and DAC Parameter
Set-Up
Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
Easily Configured via GUI in Libero
®
System-on-Chip
(SoC) Software
FPGA I/Os
– LVDS, PCI, PCI-X, up to 24 mA IOH/IOL
– Up to 350 MHz
MSS I/Os
– Schmitt Trigger, up to 6 mA IOH, 8 mA IOL
– Up to 180 MHz
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
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Analog Compute Engine (ACE)
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I/Os and Operating Voltage
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High-Performance FPGA
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1 Theoretical maximum
2 A2F500 devices
September 2012
© 2012 Microsemi Corporation
I
Military Grade SmartFusion Customizable System-on-Chip (cSoC)
SmartFusion cSoC Family Product Table
SmartFusion
®
cSoC
FPGA Fabric
System Gates
Tiles (D-flip-flops)
RAM Blocks (4,608 bits)
Microcontroller
Subsystem (MSS)
Flash (Kbytes)
SRAM (Kbytes)
Cortex-M3 with memory protection unit (MPU)
10/100 Ethernet MAC
External Memory Controller (EMC)
DMA
I
2
C
SPI
16550 UART
32-Bit Timer
PLL
32 KHz Low Power Oscillator
100 MHz On-Chip RC Oscillator
Main Oscillator (32 KHz to 20 MHz)
Programmable Analog
ADCs (8-/10-/12-bit SAR)
DACs (12-bit sigma-delta)
Signal Conditioning Blocks (SCBs)
Comparator
2
Current Monitors
2
Temperature Monitors
2
Bipolar High Voltage Monitors
2
1
1
1
2
1
1
2
1
1
1
1
3
3
3
3
5
3
10
3
5
3
5
3
10
3
No
8 Ch
2
2
2
2
2
1
A2F060
60,000
1,536
8
128
16
Yes
Yes
24-bit address,16-bit data
A2F500
500,000
11,520
24
512
64
Notes:
1. Two PLLs are available in FG484 (one PLL in FG256).
2. These functions share I/O pins and may not all be available at the same time. See the "Analog Front-End Overview" section in
the
SmartFusion Programmable Analog User’s Guide
for details.
3. Available on FG484 only.
II
R ev i si o n 1
Medical Electronics
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