MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3874 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3874 group includes data link layer communication control cir-
cuit, A-D converters, D-A converter, automatic data transfer serial
I/O, UART, and watchdog timer etc.
The various microcomputers in the 3874 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3874 group, re-
fer to the section on group expansion.
FEATURES
qBasic
machine-language instructions ...................................... 71
qMinimum
instruction execution time ................................. 0.32
µs
(at 6.4 MHz oscillation frequency, in double-speed mode)
qMemory
size
ROM ............................................................... 16 K to 60 K bytes
RAM ............................................................... 1024 to 2048 bytes
qProgrammable
input/output ports ............................................ 72
qInput
port .................................................................................... 1
qInterrupts
................................................. 27 sources, 16 vectors
(Interrupt source discrimination register exists, included key in-
put interrupt)
qTimer
1, timer 2, timer 3 ................................................. 8-bit
!
3
qTimer
X, timer Y............................................................ 16-bit
!
2
qSerial
I/O1 .................... 8-bit
!
1(UART or Clock-synchronized)
qSerial
I/O2 ................................... 8-bit
!
1(Clock-synchronized)
qSerial
I/O3 ...................................................................... 8-bit
!
1
(Clock-synchronized automatic data transfer/arbitrary bit trans-
fer function available)
qA-D
converter ................................................. 8-bit
!
8 channels
qD-A
converter ................................................... 8-bit
!
1 channel
qData
link layer communication control circuit ............................ 1
qClock
generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
qWatchdog
timer ............................................................ 20-bit
!
1
qPower
source voltage ................................................ 3.0 to 5.5 V
qPower
dissipation
In double-speed mode ...................................................... 90 mW
In high-speed mode .......................................................... 60 mW
(at 32 kHz oscillation frequency, at 5 V power source voltage)
In low-speed mode .......................................................... 180
µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
qOperating
temperature range .................................... –40 to 85°C
(Extended operating temperature version and automotive ver-
sion)
APPLICATION
Automotive comfort control for audio system, air conditioning etc.,
automotive body electronics control, household appliances, and
other consumer applications, etc.
MITSUBISHI MICROCOMPUTERS
3874 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
V
CC
, V
SS
V
REF
AV
SS
RESET
X
IN
Name
Power source input
Reference voltage input
Analog power source
input
Reset input
Clock input
Functions
•Apply voltage of 3.0 V – 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D and D-A conver ters.
•Analog power source input pin for A-D and D-A converters.
•Connect to V
SS
.
•Reset input pin for active “L.”
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the X
IN
and X
OUT
pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
•Feedback resistor is built in between X
IN
pin and X
OUT
pin.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Sub-clock generating circuit I/O
pins connect a resonator.
(This circuit cannot be operated by
an external clock.)
•Interrupt input pins
•Serial I/O1 function pins
Function except a port function
X
OUT
P0
0
–P0
7
P1
0
–P1
7
P2
0
–P2
7
P3
0
–P3
7
P4
0
/X
COUT
,
P4
1
/X
CIN
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
P4
2
/INT
1
,
I/O port P4
P4
3
/INT
2
P4
4
/R
X
D,
P4
5
/T
X
D,
P4
6
/S
CLK1
,
P4
7
/S
RDY1
P5
0
/T
OUT
P5
1
/INT
3
–
P5
3
/INT
5
P5
4
/CNTR
0
,
P5
5
/CNTR
1
P5
6
/RTP
0
,
P5
7
/RTP
1
•8-bit I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•Timer 2 output pin
•Interrupt input pins
•Timer X, timer Y function pins
•Real time port function pins
I/O port P5
5
EE_FPGA Learning Park
京公网安备 11010802033920号
EEWORLD
