5440DMQB datasheet, PDF - EEWORLD Datasheet

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5440DMQB: DescriptionIC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate; Categorylogic logic; File Size55KB，3 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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5440DMQB Overview

IC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate

5440DMQB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	National Semiconductor（TI ）
package instruction	CERAMIC, DIP-14
Reach Compliance Code	unknown
Other features	IOL = 48MA @ VOL = 0.4V; IOH = 1.2MA @ VOH = 2.4V
series	TTL/H/L
JESD-30 code	R-GDIP-T14
JESD-609 code	e0
length	19.43 mm
Load capacitance (CL)	15 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.048 A
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	OPEN-COLLECTOR
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	27 mA
Prop。Delay @ Nom-Sup	22 ns
propagation delay (tpd)	22 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

5440DMQB Related Products

	5440DMQB	DM7440N	DM5440J
Description	IC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate	IC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, PDIP14, DIP-14, Gate	IC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	National Semiconductor（TI ）	National Semiconductor（TI ）	National Semiconductor（TI ）
package instruction	CERAMIC, DIP-14	DIP, DIP14,.3	DIP, DIP14,.3
Reach Compliance Code	unknown	unknown	unknown
series	TTL/H/L	TTL/H/L	TTL/H/L
JESD-30 code	R-GDIP-T14	R-PDIP-T14	R-GDIP-T14
JESD-609 code	e0	e0	e0
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	0.048 A	0.048 A	0.048 A
Number of functions	2	2	2
Number of entries	4	4	4
Number of terminals	14	14	14
Maximum operating temperature	125 °C	70 °C	125 °C
Minimum operating temperature	-55 °C	-	-55 °C
Package body material	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
encapsulated code	DIP	DIP	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V	5 V
Maximum supply current (ICC)	27 mA	27 mA	27 mA
Prop。Delay @ Nom-Sup	22 ns	22 ns	22 ns
propagation delay (tpd)	22 ns	22 ns	22 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO
Maximum seat height	5.08 mm	5.08 mm	5.08 mm
Maximum supply voltage (Vsup)	5.5 V	5.25 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.75 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V
surface mount	NO	NO	NO
technology	TTL	TTL	TTL
Temperature level	MILITARY	COMMERCIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	7.62 mm	7.62 mm
Other features	IOL = 48MA @ VOL = 0.4V; IOH = 1.2MA @ VOH = 2.4V	IOL = 48MA @ VOL = 0.4V; IOH = 0.4MA @ VOH = 2.4V	-
length	19.43 mm	19.18 mm	-
Load capacitance (CL)	15 pF	15 pF	-
Base Number Matches	1	1	-

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