revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V216A is a family of low voltage 2-Mbit static RAMs
organized as 131,072-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.25µm CMOS technology.
The M5M5V216A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V216ATP (normal lead bend type package)
, M5M5V216ART (reverse lead bend type package) , both types
are very easy to design a printed circuit board.
From the point of operating temperature, the family is divided into
three versions; "Standard", "W-version", and "I-version". Those are
summarized in the part name table below.
FEATURES
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,typ.)
No clocks, No refresh
Data retention supply voltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S , BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prevents data contention in the I/O bus
Process technology: 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
PART NAME TABLE
Version,
Operating
temperature
Part name
M5M5V216ATP , RT -55L
Power
Supply
2.7 ~ 3.6V
2.7 ~ 3.6V
Access
time
Stand-by current Icc
(PD)
, Vcc=3.0V
typical *
Ratings (max.)
25 C
---
40 C
---
25 C
---
1µA
40 C
---
3µA
70 C
20µA
8µA
85 C
---
---
max.
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
Active
current
Icc1
(3.0V, typ.)
Standard
0 ~ +70 C
M5M5V216ATP , RT -70L
M5M5V216ATP , RT -55H
M5M5V216ATP , RT -70H
M5M5V216ATP , RT -55LW
0.3µA 1µA
W-
version
-20 ~ +85 C
M5M5V216ATP , RT -70LW
M5M5V216ATP , RT -55HW
M5M5V216ATP , RT -70HW
M5M5V216ATP , RT -55L I
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
55ns(@ 2.7V) / 50ns(@3.3V)
70ns(@ 2.7V) / 65ns(@3.3V)
---
---
---
1µA
---
1µA
---
3µA
---
3µA
20µA 50µA
8µA
24µA
45mA
(10MHz)
5mA
(1MHz)
0.3µA 1µA
---
---
I-
version
-40 ~ +85 C
M5M5V216ATP , RT -70L I
M5M5V216ATP , RT -55H I
M5M5V216ATP , RT -70H I
20µA 50µA
8µA
24µA
0.3µA 1µA
PIN CONFIGURATION
A4
A3
A2
A1
A0
S
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
* "typical" parameter is sampled, not 100% tested.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
A5
A6
A7
OE
BC2
BC1
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
S
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
Pin
A0 ~ A16
S
W
OE
BC1
BC2
Vcc
GND
Function
Address input
Chip select input
Write control input
Output inable input
Lower Byte (DQ1 ~ 8)
Upper Byte (DQ9 ~ 16)
Power supply
Ground supply
DQ1 ~ DQ16 Data input / output
Outline: TP :
44P3W - H
RT : 44P3W - J
NC: No Connection
MITSUBISHI ELECTRIC
1
revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V216ATP,RT is organized as 131,072-words by
16-bit. These devices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low
level S. The address(A0~A16) must be set up before the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S are in
an active state(S=L).
When setting BC1 at the high level and other pins are in
an active stage , upper-byte are in a selesctable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high level and other pins are in an active stage, lower-
byte are in a selectable mode and upper-byte are in a
non-selectable mode.
When setting BC1 and BC2 at a high level or S at a high
level, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S.
The power supply current is reduced as low as 0.3µA(25 C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S BC1 BC2 W OE
H
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
H
H
H
L
L
L
X
H
H
H
H
L
L
L
L
L
L
X
X
L
H
H
L
H
H
L
H
H
X
X
X
L
H
X
L
H
X
L
H
Write
Read
Write
Read
Mode
Non selection
Non selection
DQ1~8
DQ9~16
Icc
High-Z High-Z Standby
High-Z High-Z Standby
Din
Dout
High-Z
High-Z
Din
Dout
High-Z
High-Z
Din
Dout
Din
Dout
Active
Active
Active
Active
Active
Active
Active
Active
Active
Write
Read
High-Z High-Z
High-Z High-Z
BLOCK DIAGRAM
A
0
A
1
MEMORY ARRAY
131072 WORDS
x 16 BITS
A
15
A
16
CLOCK
GENERATOR
High-Z High-Z
DQ
1
DQ
8
-
DQ
9
DQ
16
S
BC1
BC2
W
GND
OE
Vcc
MITSUBISHI ELECTRIC
2
revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
temperature
Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25 C
Standard
W-version
I-version
(-L, -H)
(-LW, -HW)
(-LI, -HI)
Ratings
Units
Vcc
V
I
V
O
P
d
T
a
T
stg
-0.5
*
~ +4.6
-0.5
*
~ Vcc + 0.5
0 ~ Vcc
700
0 ~ +70
- 20 ~ +85
- 40 ~ +85
- 65 ~ +150
V
mW
C
C
* -3.0V in case of AC (Pulse width < 30ns)
=
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
High-level input voltage
Low-level input voltage
Conditions
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Min
Typ
Max
Vcc+0.3V
Units
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Icc
1
Icc
2
I
OH
= -0.5mA
High-level output voltage 2
I
OH
= -0.05mA
I
OL
=2mA
Low-level output voltage
V
I
=0
~
Vcc
Input leakage current
High-level output voltage 1
Output leakage current
Active supply current
( AC,MOS level )
Active supply current
( AC,TTL level )
BC1 and BC2=V
IH
or S=V
IH
or OE=V
IH
, V
I/O
=0 ~ Vcc
BC1 and BC2
<
0.2V , S
<
0.2V
=
=
>
other inputs
<
0.2V or
=
Vcc-0.2V
=
Output - open (duty 100%)
BC1 and BC2=V
IL
, S=V
IL
other pins =V
IH or
V
IL
Output - open (duty 100%)
<1>
>
S
=
Vcc - 0.2V,
2.0
-0.3 *
2.4
Vcc-0.5V
0.6
V
0.4
±1
±1
µA
f= 10MHz
f= 1MHz
f= 10MHz
f= 1MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
45
5
45
5
-
-
-
-
1
0.3
0.3
0.3
-
60
15
60
15
60
25
30
10
5
2
2
2
0.5
mA
-LW, -LI
-L, -LW, -LI
-HW, -HI
-H, -HW, -HI
-H
-HW
-HI
+70 ~ +85 C
+70 C
+70 ~ +85 C
+40 ~ +70 C
+25 ~ +40 C
0 ~ +25 C
- 20 ~ +25 C
- 40 ~ +25 C
other inputs = 0 ~ Vcc
Icc
3
Stand by supply current
( AC,MOS level )
<2>
>
BC1 and BC2
=
Vcc - 0.2V
µA
S
<
0.2V
=
Other inputs=0~Vcc
Icc
4
Stand by supply current
( AC,TTL level )
BC1 and BC2=V
IH ,
S=V
IL
Other inputs= 0 ~ Vcc
or
S=V
IH
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25 C
* -3.0V in case of AC (Pulse width < 30ns)
=
CAPACITANCE
Symbol
Parameter
Input capacitance
Output capacitance
Conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=
GND,V
O
=25mVrms, f=1MHz
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Typ
Units
Min
Max
C
I
C
O
8
10
pF
MITSUBISHI ELECTRIC
3
revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply voltage
Input pulse
Input rise time and fall time
Reference level
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
2.7V~3.6V
V
IH
=2.2V,V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Transition is measured ±500mV from
steady state voltage.(for t
en
,t
dis
)
1TTL
DQ
CL
Including scope and
jig capacitance
Output loads
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
t
CR
Parameter
Read cycle time
Address access time
Chip select access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S high
Output disable time after BC1 high
Output disable time after BC2 high
Output disable time after OE high
Output enable time after S low
Output enable time after BC1 low
Output enable time after BC2 low
Output enable time after OE low
Data valid time after address
M5M5V216ATP,RT - 55
M5M5V216ATP,RT - 70
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
55
Max
55
55
55
55
30
20
20
20
20
Min
70
Max
70
70
70
70
35
25
25
25
25
t
a
(A)
t
a
(S)
t
a
(BC1)
t
a
(BC2)
t
a
(OE)
t
dis
(S)
t
dis
(BC1)
t
dis
(BC2)
t
dis
(OE)
t
en
(S)
t
en
(BC1)
t
en
(BC2)
t
en
(OE)
t
V
(A)
10
10
10
5
10
10
10
10
5
10
(3) WRITE CYCLE
Limits
Symbol
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
M5M5V216ATP,RT - 55
M5M5V216ATP,RT - 70
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(BC1)
t
su
(BC2)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
Min
55
45
0
50
50
50
50
25
0
0
Max
Min
70
55
0
65
65
65
65
30
0
0
Max
20
20
5
5
5
5
25
25
MITSUBISHI ELECTRIC
4
revision-01, ' 98.12.08
MITSUBISHI LSIs
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
A
0~16
t
CR
t
a
(A)
BC1
and / or
t
v
(A)
t
a
(BC1)
(Note3)
or
t
a
(BC2)
(Note3)
BC2
t
dis
(BC1) or
t
dis
(BC1)
t
a
(S)
S
(Note3)
t
dis
(S)
t
a
(OE)
(Note3)
OE
(Note3)
W = "H" level
t
en
(OE)
t
en
(BC1)
t
en
(BC2)
t
en
(S)
t
dis
(OE)
(Note3)
DQ
1~16
VALID DATA
Write cycle ( W control mode )
t
CW
A
0~16
t
su
(BC1) or
t
su
(BC2)
BC1
and / or
BC2
(Note3)
t
su
(S)
(Note3)
S
(Note3)
t
su
(A-WH)
(Note3)
OE
t
su
(A)
W
t
dis
(OE)
DQ
1~16
DATA IN
STABLE
t
w
(W)
t
dis
(W)
t
rec
(W)
t
en
(OE)
t
en
(W)
t
su
(D)
t
h
(D)
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