5962F9671402V9A datasheet, PDF

5962F9671402V9A: DescriptionACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16; Categorylogic logic; File Size155KB，3 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16

Parameter Name	Attribute value
Parts packaging code	DIE
package instruction	DIE,
Contacts	16
Reach Compliance Code	unknown
series	ACT
JESD-30 code	S-XUUC-N16
JESD-609 code	e0
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	UNSPECIFIED
encapsulated code	DIE
Package shape	SQUARE
Package form	UNCASED CHIP
propagation delay (tpd)	26 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	NO LEAD
Terminal location	UPPER
total dose	300k Rad(Si) V
Trigger type	NEGATIVE EDGE
minfmax	60 MHz
Base Number Matches	1

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