HD74HCT623FP-EL datasheet, PDF

HD74HCT623FP-EL: DescriptionHCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, FP-20DA; Categorylogic logic; File Size57KB，9 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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HD74HCT623FP-EL Overview

HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, FP-20DA

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	SOP,
Contacts	20
Reach Compliance Code	unknown
series	HCT
JESD-30 code	R-PDSO-G20
length	12.6 mm
Logic integrated circuit type	BUS TRANSCEIVER
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	25 ns
Certification status	Not Qualified
Maximum seat height	2.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5.5 mm
Base Number Matches	1

HD74HCT620/HD74HCT623

Octal Bus Transceivers (with inverted 3-state outputs)/

Octal Bus Transceivers (with 3-state outputs)

Description

This octal transceiver is designed for asynchronous two-way communication between data buses. The

control function implementation allows for maximum flexibility in timng.

This device allows data transmission from A bus to the B bus or from the B bus to the A bus depending

upon the logic levels at the enable inputs (GBA and GAB).

The enable inputs can be used to disable the device so that the buses are affectively isolated.

The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of

GBA

and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control

inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of

bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will

be identical for the HD74HCT623 or complementary for the HD74HCT620.

Features

•

LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility

High Speed Operation: t

(Bus to Bus) = 15 ns typ (C

= 50 pF)

High Output Current: Fanout of 15 LSTTL Loads

Wide Operating Voltage: V

= 4.5 to 5.5 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I

(static) = 4 µA max (Ta = 25°C)

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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