SI5335C-B02795-GM datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> SI5335C-B02795-GM

SI5335C-B02795-GM: DescriptionClock Generator; CategoryThe embedded processor and controller Microcontrollers and processors; File Size362KB，46 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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SI5335C-B02795-GM Overview

Clock Generator

SI5335C-B02795-GM Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	HVQCCN,
Reach Compliance Code	unknown
Other features	ALSO OPERATES WITH 2.5V AND 3.3V NOMINAL SUPPLY
JESD-30 code	S-XQCC-N24
JESD-609 code	e4
length	4 mm
Humidity sensitivity level	3
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	350 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	350 MHz
Maximum seat height	0.9 mm
Maximum supply voltage	1.98 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches	1

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Si5335

-C

USTOMIZABLE

, A

- F

REQUENCY

, A

- O

U TP U T

UAD

LOCK

ENERATOR

U FF E R

Features



CLK0A

CLK0B

VDD

VDDO0



RSVD_GND



Low power MultiSynth™ technology

enables independent, any-frequency

synthesis of four frequencies

Configurable as a clock generator or

clock buffer device

Three independent, user-assignable,

pin-selectable device configurations

Highly-configurable output drivers with

up to four differential outputs, eight

single-ended clock outputs, or a

combination of both

Low phase jitter of 0.7 ps RMS

Flexible input reference:



External crystal: 25 or 27 MHz



CMOS input: 10 to 200 MHz



SSTL/HSTL input: 10 to 350 MHz



Differential input: 10 to 350 MHz

Independently configurable outputs

support any frequency or format:



LVPECL/LVDS/CML: 1 to 350 MHz



HCSL: 1 to 250 MHz



CMOS: 1 to 200 MHz



SSTL/HSTL: 1 to 350 MHz

Independent output voltage per driver:

1.5, 1.8, 2.5, or 3.3 V



Single supply core with excellent

PSRR: 1.8, 2.5, 3.3 V

Up to five user-assignable pin

functions simplify system design:

SSENB (spread spectrum control),

RESET, Master OEB or OEB per pin,

and Frequency plan select

(FS1, FS0)

Loss of signal alarm

PCIe-compliant spread spectrum

clocking (SSC):



100 MHz



0.5% down spread



31.5 kHz modulation rate

Two selectable loop bandwidth

settings: 1.6 MHz or 475 kHz

Easy to customize with web-based

utility

Small size: 4 x 4 mm, 24-QFN

Low power (core):



45 mA (PLL mode)



12 mA (Buffer mode)

Wide temperature range: –40 to

+85 °C

Ordering Information:

See page 41.

Pin Assignments

Top View

CLK1A

CLK1B

VDDO1

VDDO2

CLK2A

CLK2B

XA/CLKIN

XB/CLKINB

GND

Pad

Applications



Ethernet switch/router

PCI Express 3.0/2.1/1.1

PCIe jitter attenuation

DSL jitter attenuation

Broadcast video/audio timing



Processor and FPGA clocking

MSAN/DSLAM/PON

Fibre Channel, SAN

Telecom line cards

1 GbE and 10 GbE

Description

The Si5335 is a highly flexible clock generator capable of synthesizing four

completely non-integer-related frequencies up to 350 MHz. The device has four

banks of outputs with each bank supporting one differential pair or two single-ended

outputs. Using Silicon Laboratories' patented MultiSynth fractional divider

technology, all outputs are guaranteed to have 0 ppm frequency synthesis error

regardless of configuration, enabling the replacement of multiple clock ICs and

crystal oscillators with a single device. The Si5335 supports up to three independent,

pin-selectable device configurations, enabling one device to replace three separate

clock generators or buffer ICs. To ease system design, up to five user-assignable

and pin-selectable control pins are provided, supporting PCIe-compliant spread

spectrum control, master and/or individual output enables, frequency plan selection,

and device reset. Two selectable PLL loop bandwidths support jitter attenuation in

applications, such as PCIe and DSL. Through its flexible ClockBuilder™

(www.silabs.com/ClockBuilder) web configuration utility, factory-customized, pin-

controlled devices are available in two weeks without minimum order quantity

restrictions.

Rev. 1.2 1/13

VDDO3

VDD

CLK3B

CLK3A

LOS

Si5335

Si5335

ABLE

Section

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical PCIe System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2. MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3. ClockBuilder Web-Customization Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.6. Multi-Function Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8. Frequency Select/Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.9. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.10. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

8. Loop Bandwidth Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9. Applications of the Si5335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

9.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.3. Configurable Universal Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . 37

10. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

14.1. Si5335 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Rev. 1.2

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