MX26L12811MC-12 datasheet, PDF

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MX26L12811MC-12: DescriptionFlash, 8MX16, 120ns, PDSO44, 0.500 INCH, PLASTIC, MO-175, SOP-44; Categorystorage storage; File Size369KB，32 Pages; ManufacturerMacronix; Websitehttp://www.macronix.com/en-us/Pages/default.aspx

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MX26L12811MC-12 Overview

Flash, 8MX16, 120ns, PDSO44, 0.500 INCH, PLASTIC, MO-175, SOP-44

MX26L12811MC-12 Parametric

Parameter Name	Attribute value
Maker	Macronix
Parts packaging code	SOIC
package instruction	SOP,
Contacts	44
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum access time	120 ns
Spare memory width	8
JESD-30 code	R-PDSO-G44
length	28.5 mm
memory density	134217728 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of terminals	44
word count	8388608 words
character code	8000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	3 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	12.6 mm
Base Number Matches	1

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MX26L12811MC

128M [x8/x16] SINGLE 3V PAGE MODE MTP MEMORY

FEATURES

• 3.0V to 3.6V operation voltage

• Block Structure

- 128 x 128Kbyte Erase Blocks

• Fast random / page mode access time

- 120/25 ns Read Access Time (page depth:4-word)

• 32-Byte Write Buffer

- 6 us/byte Effective Programming Time

• High Performance

- Block erase time: 2s typ.

- Byte programming time: 210us typ.

- Block programming time: 0.8s typ. (using Write to

Buffer Command)

• Program/Erase Endurance cycles: 10 cycles

Packaging

Performance

• Low power dissipation

- typical 15mA active current for page mode read

- 80uA/(max.) standby current

- 44-Lead SOP

Technology

- Nbit (0.25u) MTP Technology

GENERAL DESCRIPTION

The MXIC's MX26L12811MC series MTP use the most

advance 2 bits/cell Nbit technology, double the storage

capacity of memory cell. The device provide the high

density MTP memory solution with reliable performance

and most cost-effective.

The device organized as by 8 bits or by 16 bits of output

bus. The device is packaged in 44-Lead SOP. It is de-

signed to be reprogrammed and erased in system or in

standard EPROM programmers.

The device offers fast access time and allowing opera-

tion of high-speed microprocessors without wait states.

The device augment EPROM functionality with in-circuit

electrical erasure and programming. The device uses a

command register to manage this functionality.

The MXIC's Nbit technology reliably stores memory con-

tents even after the specific erase and program cycles.

The MXIC cell is designed to optimize the erase and

program mechanisms by utilizing the dielectric's charac-

ter to trap or release charges from ONO layer.

The device uses a 3.0V to 3.6V VCC supply to perform

the High Reliability Erase and auto Program/Erase algo-

rithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

P/N:PM0990

REV. 1.0, OCT. 29, 2003

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