CY7C1146V18-300BZXC datasheet, PDF

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CY7C1146V18-300BZXC: DescriptionDDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165; Categorystorage storage; File Size451KB，27 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY7C1146V18-300BZXC Overview

DDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

CY7C1146V18-300BZXC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	300 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	16777216 bit
Memory IC Type	DDR SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.25 A
Minimum standby current	1.7 V
Maximum slew rate	0.85 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	13 mm
Base Number Matches	1

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

18-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

■

Functional Description

The CY7C1146V18, CY7C1157V18, CY7C1148V18, and

CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1146V18) or 9-bit words (CY7C1157V18) or 18-bit

words (CY7C1148V18) or 36-bit words (CY7C1150V18) that

burst sequentially into or out of the device.

Asynchronous inputs include output impedance matching input

(ZQ). Synchronous data outputs (Q, sharing the same physical

pins as the data inputs D) are tightly matched to the two output

echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

300 MHz to 375 MHz clock for high bandwidth

2-Word burst for reducing address bus frequency

Double Data Rate (DDR) interfaces

(data transferred at 750 MHz) at 375 MHz

Read latency of 2.0 clock cycles

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

Data valid pin (QVLD) to indicate valid data on the output

Synchronous internally self-timed writes

Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

DD[1]

■

HSTL inputs and Variable drive HSTL output buffers

■

Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■

Offered in both Pb-free and non Pb-free packages

■

JTAG 1149.1-compatible test access port

Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1146V18 – 2M x 8

CY7C1157V18 – 2M x 9

CY7C1148V18 – 1M x 18

CY7C1150V18 – 512K x 36

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

375 MHz

375

1020

333 MHz

333

920

300 MHz

300

850

Unit

MHz

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06621 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised March 06, 2008

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