MC14562B
128-Bit Static Shift
Register
The MC14562B is a 128–bit static shift register constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired.
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•
•
•
•
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Diode Protection on All Inputs
Fully Static Operation
Cascadable to Provide Longer Shift Register Lengths
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MARKING
DIAGRAMS
14
PDIP–14
P SUFFIX
CASE 646
MC14562BCP
AWLYYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 1.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 2.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±
10
500
– 55 to +125
– 65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
ORDERING INFORMATION
Device
MC14562BCP
Package
PDIP–14
Shipping
25/Rail
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
v
v
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14562B/D
MC14562B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Characteristic
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
V
IH
5.0
10
15
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
—
5.0
10
15
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
—
—
—
—
—
—
—
—
—
—
—
—
±
0.1
—
5.0
10
20
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
—
—
—
—
—
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
±
0.00001
5.0
0.010
0.020
0.030
—
—
—
—
—
—
—
±
0.1
7.5
5.0
10
20
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
—
—
—
—
—
—
—
—
—
—
—
—
±
1.0
—
150
300
600
mAdc
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
mAdc
Min
—
—
—
– 55
_
C
25
_
C
125
_
C
Max
Min
—
—
—
Typ
(3.)
0
0
0
Max
Min
—
—
—
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
“0” Level
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
“0” Level
(V
O
= 4.5 or 05 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current
(4.) (5.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
V
IL
—
—
—
—
—
—
2.25
4.50
6.75
—
—
—
V
OH
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Vdc
Sink
I
in
C
in
I
DD
µAdc
pF
µAdc
I
T
I
T
= (1.94
µA/kHz)
f + I
DD
I
T
= (3.81
µA/kHz)
f + I
DD
I
T
= (5.52
µA/kHz)
f + I
DD
µAdc
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25
_
C.
5. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
µA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.004.
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MC14562B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(6.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
Min
—
—
—
Typ
(7.)
100
50
40
Max
200
100
80
Unit
ns
Propagation Delay Time
Clock to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 515 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 217 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 145 ns
Clock Pulse Width
(50% Duty Cycle)
Clock Pulse Frequency
t
PLH
,
t
PHL
5.0
10
15
t
WH
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
—
—
—
600
220
150
—
—
—
– 20
– 10
0
– 20
– 10
0
350
165
155
350
200
140
—
—
—
600
250
170
300
110
75
1.9
5.6
8.0
– 170
– 64
– 60
– 91
– 58
– 48
263
109
100
267
140
93
—
—
—
1200
500
340
—
—
—
1.1
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
15
5
4
ns
ns
f
cl
MHz
Data to Clock Setup Time
t
su(1)
ns
t
su(0)
ns
Data to Clock Hold Time
t
h(1)
ns
t
h(0)
ns
Clock Input Rise and Fall Times
t
r
, t
f
µs
6. The formulas given are for the typical characteristics only at 25
_
C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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