LTC1/815152JTP datasheet, PDF - EEWORLD Datasheet

LTC1/815152JTP: DescriptionPTC Thermistor, 1500ohm, Surface Mount, CHIP; CategoryPassive components The resistor; File Size54KB，2 Pages; ManufacturerKamaya; Environmental Compliance

Download Datasheet Parametric View All

LTC1/815152JTP Overview

PTC Thermistor, 1500ohm, Surface Mount, CHIP

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Kamaya
package instruction	,
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-609 code	e3
Manufacturer's serial number	LTC
Installation features	SURFACE MOUNT
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package shape	RECTANGULAR PACKAGE
method of packing	TAPE, PAPER
Rated (AC) voltage (URac)	100 V
Rated power dissipation(P)	0.125 W
Rated temperature	70 °C
resistance	1500 Ω
Resistor type	PTC THERMISTOR
surface mount	YES
Terminal surface	Tin (Sn)
Terminal location	DUAL ENDED
Terminal shape	WRAPAROUND
Thermistor Applications	OVERLOAD PROTECTION
Tolerance	5%
Base Number Matches	1

[EVK-NINA-B400 Evaluation Kit] + First Meeting: [i=s]This post was last edited by damiaa on 2021-5-14 11:34[/i][EVK-NINA-B400 Evaluation Kit] + First Meeting I got the EVK-NINA-B400 a few days ago. I made some preparations over the weekend and toda...; damiaa RF/Wirelessly

Core materials for high frequency magnetic components: Core materials for high frequency magnetic components...; zbz0529 Test/Measurement

msp430 LCD driver module: 1. Power saving (because the liquid crystal itself does not emit light, the power consumption is low) 2. Can only be driven by low-frequency AC voltage, DC will damage the LCD 3. Types: segment LCD, c...; 火辣西米秀 Microcontroller MCU

EEWORLD University Hall----Combining buck-boost topology and USB Type C? Power Delivery to achieve maximum power density: Combining buck-boost topology with USB Type C? Power Delivery to achieve maximum power density : https://training.eeworld.com.cn/course/27353...; hi5 Talking

Questions about FPGA configuration: As shown in Figure 1, are unused pins configured as "three-state input input" or "three-state input plus weak pull-up"? In Figure 2, why are these dual_purpose_pins set to "use as regular IO"? They ar...; 平漂流 EE_FPGA Learning Park

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ