BUS-61555-120Y datasheet, PDF - EEWORLD Datasheet

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BUS-61555-120Y: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, DDIP-78; CategoryThe embedded processor and controller Microcontrollers and processors; File Size49KB，4 Pages; ManufacturerData Device Corporation

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BUS-61555-120Y Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, DDIP-78

BUS-61555-120Y Parametric

Parameter Name	Attribute value
Maker	Data Device Corporation
Parts packaging code	QIP
package instruction	QIP,
Contacts	78
Reach Compliance Code	unknown
Address bus width	16
boundary scan	NO
letter of agreement	MIL-STD-1553
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-XQIP-P78
low power mode	NO
Number of serial I/Os	2
Number of terminals	78
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	UNSPECIFIED
encapsulated code	QIP
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
Filter level	MIL-STD-883 Class B
Maximum seat height	5.334 mm
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	QUAD
width	41.91 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
Base Number Matches	1

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BUS-61553

MIL-STD-1553 ADVANCED INTEGRATED

MUX (AIM ) HYBRID

ALSO

SEE

IDE

R’S GU

USE

DESCRIPTION

DDC’s

BUS-61553

Advanced

Integrated Mux (AIM) Hybrid is a

complete

MIL-STD-1553

Bus

Controller (BC), Remote Terminal

Unit (RTU), and Bus Monitor (MT)

device. Packaged in a single 78-pin

DIP package, the BUS-61553 con-

tains dual low-power transceivers,

complete BC/RT/MT protocol logic, a

MIL-STD-1553-to-host interface unit

and 8K x 16 RAM.

Using an industry standard dual

transceiver and standard status and

control signals, the BUS-61553 sim-

plifies system integration at both the

MIL-STD-1553 and host processor

interface levels.

All 1553 operations are controlled

through the CPU access to the

shared 8K x 16 RAM. To ensure

maximum design flexibility, memory

control lines are provided for attach-

ing external RAM to the BUS-61553

address and data buses and for dis-

abling internal memory; the total

combined memory space can be

expanded to 64K x 16. All 1553 trans-

fers are entirely memory-mapped;

thus the CPU interface requires

minimal hardware and/or software

support.

The BUS-61553 operates over the

full military -55°C to +125°C temper-

ature range. Available screened to

MIL-PRF-38534, the BUS-61553 is

ideal for demanding military and

industrial microprocessor-to-1553

interface applications.

FEATURES

• Fully Intergrated Terminal

Including:

–Dual Transceiver

–BC/RT/MT Protocol

–Memory Management Unit

–Processor lnterface Logic

–8K x 16 RAM

• CMOS and Bipolar Technologies

• Internal Interrupt Status and Time

Tag Registers

• High Reliability

• 883B Processing Available

BUS-25679

DATA

BUS A

TRANSCEIVER A

TX INH

CONTENTION

RESOLVER

INTERRUPT

GENERATOR

CLOCK IN

CHANNEL A

ENCODER/

DECODER

MEMORY

TIMING

CPU

TIMING

MSTRCLR

SELECT

STRBD

READYD

RD/WR

MEM/REG

EXTEN

EXTLD

INT

TRANSFORMER A

768

µs

TIME OUT

PROTOCOL

CONTROLLER

A15-A00

BUS-25679

DATA

BUS B

TX INH

TRANSCEIVER B

D15-D00

TRANSFORMER B

CHANNEL B

ENCODER/

DECODER

8K x 16

SHARED RAM

PARITY

CHECKER

RT ADDR

RTAD0

RTAD1

RTAD2

RTAD3

RTAD4

RTAD P

RTPARERR

RAM

FIGURE 1. BU-61553 BLOCK DIAGRAM

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