CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
1. This device contains circuitry to protect the inputs against damage due to high static voltages of electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For
proper operation it is recommended that V
IN
and V
OUT
be constrained to the range V
SS
<(V
IN
or V
OUT
)<V
DD
. Reliability of operation is
enhanced if unused inputs except OSC2 are connected to an appropriate logic voltage level (e.g., either V
SS
or V
DD
).
9-101
HIP7038A8
Functional Description
The HIP7038A8 MCU is functionally identical to the
HIP7030A2 and HIP7030A8 microcontrollers. The device
differs only in that the on-board masked ROM has been
replaced with EEPROM, which allows the device to be
rapidly programmed by the user. For detailed information
about the functions included on the HIP7038A8 refer to File
Number 3646, the technical specification of the HIP7030A2
Microcontroller. Only differences are presented here.
The availability of the HIP7038A8 dramatically reduces the
time-to-market of new products by providing the develop-
ment engineer rapid feedback during the design phase of a
HIP7030A2/8 project.
The EEPROM is reusable and can be reprogrammed up to
10
4
times.
$0000
I/O
32 BYTES
0000
PORTS
1 BYTE
UNUSED
2 BYTES
PORTS
2 BYTES
UNUSED
2 BYTES
PORTS
2 BYTES
UNUSED
1 BYTE
SERIAL PERIPHERAL
INTERFACE
3 BYTES
UNUSED
2 BYTES
SENDEC
INTERFACE
3 BYTES
TIMER
10 BYTES
UNUSED
1 BYTE
USER
ROM
7680 BYTES
TEST
1 BYTE
WATCHDOG
2 BYTES
0031
Memory Organization
The HIP7038A8 MCU addresses 8192 bytes of memory and
I/O registers with its program counter. Of these locations,
8184 have been implemented as shown in Figure 1. The first
256 bytes of memory (page zero) include: 24 bytes of I/O
features such as data ports, the port DDRs, Timer, serial
peripheral interface (SPI), and J1850 VPW Registers; 48
bytes of user ROM, and 176 bytes of RAM. The next 7680
bytes complete the user ROM. The Built-In-Test ROM (242
bytes) is contained in memory locations $1F00 through
$1FF1. The 14 highest address bytes contain the user
defined reset and the interrupt vectors. Eight bytes of the
lowest 32 memory locations are unused and the 176 bytes of
user RAM include up to 64 bytes for the stack. Since most
programs use only a small part of the allocated stack loca-
tions for interrupts and/or subroutine stacking purposes, the
unused bytes are usable for program data storage.
0000
PORT A DATA REGISTER
UNUSED
UNUSED
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
UNUSED
UNUSED
PORT D DATA DIRECTION REGISTER
PORT D SPECIAL FUNCTION REGISTER
UNUSED
SERIAL PERIPHERAL CONTROL REGISTER
SERIAL PERIPHERAL STATUS REGISTER
SERIAL PERIPHERAL DATA I/O REGISTER
UNUSED
UNUSED
SENDEC CONTROL REGISTER
SENDEC STATUS REGISTER
SENDEC DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE HIGH REGISTER
INPUT CAPTURE LOW REGISTER
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$001F
$0020
USER
ROM
48 BYTES
$004F
$0050
0031
0032
0079
0080
RAM
176 BYTES
$00BF
$00C0
STACK
64 BYTES
$00FF
$0100
0191
0192
0255
0256
$1EFF
$1F00
7935
7936
OUTPUT COMPARE HIGH REGISTER
OUTPUT COMPARE LOW REGISTER
COUNTER HIGH REGISTER
BUILT-IN-TEST
$1FE1
$1FE2
BUILT-IN-TEST
VECTORS
$1FF1
$1FF2
$1FFF
USER
VECTORS
14 BYTES
8177
8178
8191
COUNTER LOW REGISTER
256 BYTES
ALTERNATE COUNTER HIGH REGISTER
ALTERNATE COUNTER LOW REGISTER
UNUSED
WATCHDOG RESET REGISTER
WATCHDOG STATUS REGISTER
TEST REGISTER
(SEE NOTE)
NOTE: Accessable in test mode only.
FIGURE 1. MEMORY MAP OF THE HIP7038A8
9-102
HIP7038A8
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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