71V546S100PFG datasheet, PDF - EEWORLD Datasheet

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71V546S100PFG: DescriptionTQFP-100, Tray; Categorystorage storage; File Size415KB，22 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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71V546S100PFG Overview

TQFP-100, Tray

71V546S100PFG Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	LQFP, QFP100,.63X.87
Contacts	100
Manufacturer packaging code	PKG100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Samacsys Description	TQFP 14.0 X 20.0 X 1.4 MM
Maximum access time	5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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128K x 36, 3.3V Synchronous

IDT71V546S

SRAM with ZBT™ Feature

™

Burst Counter and Pipelined Outputs

Features

◆

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the

need to control

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

Packaged in a JEDEC standard 100-pin TQFP package

Green parts available, see Ordering Information

Functional Block Diagram

LBO

Address A [0:16]

, CE

R/W

CEN

ADV/LD

BWx

Clk

Control

128K x 36 BIT

MEMORY ARRAY

Address

Input Register

Control Logic

Mux

Sel

Clk

Clock

Output Register

Gate

3821 drw 01

DSC-3821/07

Data I/O [0:31], I/O P[1:4]

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

AUGUST 2017

71V546S100PFG Related Products

	71V546S100PFG	71V546S133PFG8	71V546S133PFGI	71V546S133PFG	71V546S133PFGI8
Description	TQFP-100, Tray	TQFP-100, Reel	TQFP-100, Tray	TQFP-100, Tray	TQFP-100, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP	TQFP	TQFP	TQFP
package instruction	LQFP, QFP100,.63X.87	QFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	QFP, QFP100,.63X.87
Contacts	100	100	100	100	100
Manufacturer packaging code	PKG100	PKG100	PKG100	PKG100	PKG100
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Samacsys Description	TQFP 14.0 X 20.0 X 1.4 MM	TQFP 14.0 X 20.0 X 1.4 MM	TQFP 14.0 X 20.0 X 1.4 MM	TQFP 14.0 X 20.0 X 1.4 MM	TQFP 14.0 X 20.0 X 1.4 MM
Maximum access time	5 ns	4.2 ns	4.2 ns	4.2 ns	4.2 ns
Maximum clock frequency (fCLK)	100 MHz	133 MHz	133 MHz	133 MHz	133 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e3	e3	e3	e3	e3
memory density	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit
Memory IC Type	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
memory width	36	36	36	36	36
Humidity sensitivity level	3	3	3	3	3
Number of functions	1	1	1	1	1
Number of terminals	100	100	100	100	100
word count	131072 words	131072 words	131072 words	131072 words	131072 words
character code	128000	128000	128000	128000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-40 °C	-40 °C
organize	128KX36	128KX36	128KX36	128KX36	128KX36
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	QFP	LQFP	LQFP	QFP
Encapsulate equivalent code	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum standby current	0.04 A	0.04 A	0.045 A	0.04 A	0.045 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.25 mA	0.3 mA	0.31 mA	0.3 mA	0.31 mA
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	MATTE TIN	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.635 mm	0.65 mm	0.65 mm	0.635 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30
Base Number Matches	1	1	1	1	1
Other features	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-
length	20 mm	-	20 mm	20 mm	-
Maximum seat height	1.6 mm	-	1.6 mm	1.6 mm	-
width	14 mm	-	14 mm	14 mm	-

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