AD9863BCPZRL-50 datasheet, PDF

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AD9863BCPZRL-50: DescriptionAnalog to Digital Converters - ADC 12-Bit Mixed-Signal Front-End Processor; Categorysemiconductor Analog mixed-signal IC; File Size968KB，41 Pages; ManufacturerADI; Websitehttps://www.analog.com

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Analog to Digital Converters - ADC 12-Bit Mixed-Signal Front-End Processor

AD9863BCPZRL-50 Parametric

Parameter Name	Attribute value
Product Category	Analog to Digital Converters - ADC
Manufacturer	ADI
RoHS	Details
Mounting Style	SMD/SMT
Package / Case	LFCSP-64
Resolution	12 bit
Number of Channels	2 Channel
Sampling Rate	50 MS/s
Input Type	Differential
Architecture	Pipeline
Reference Type	External, Internal
SNR - Signal to Noise Ratio	67 dB
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Packaging	Reel
Height	0.83 mm
Length	9 mm
Moisture Sensitive	Yes
Operating Supply Voltage	3.3 V
Product	Analog to Digital Converters
Factory Pack Quantity	2500
Width	9 mm

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Data Sheet

FEATURES

Mixed-Signal Front-End (MxFE

™

) Baseband

Transceiver for Broadband Applications

AD9863

FUNCTIONAL BLOCK DIAGRAM

VIN+A

ADC

VIN–A

VIN+B

ADC

VIN–B

I/O

INTERFACE

CONFIGURATION

BLOCK

DATA

MUX

AND

LATCH

Rx DATA

Receive path includes dual 12-bit, 50 MSPS analog-to-digital

converters with internal or external reference

Transmit path includes dual 12-bit, 200 MSPS digital-to-

analog converters with 1×, 2×, or 4× interpolation and

programmable gain control

Internal clock distribution block includes a programmable

phase-locked loop and timing generation circuitry,

allowing single-reference clock operation

24-pin flexible I/O data interface allows various interleaved

or noninterleaved data transfers in half-duplex mode and

interleaved data transfers in full-duplex mode

Configurable through register programmability or

optionally limited programmability through mode pins

Independent Rx and Tx power-down control pins

64-lead LFCSP package (9 mm × 9 mm footprint)

I/O

INTERFACE

CONTROL

FLEXIBLE

I/O BUS

[0:23]

LOW-PASS

INTERPOLATION

FILTER

IOUT+A

DAC

IOUT–A

IOUT+B

DAC

IOUT–B

ADC CLOCK

DATA

LATCH

AND

DEMUX

Tx DATA

CLKIN1

CLOCK

GENERATION

BLOCK

DAC CLOCK

PLL

CLKIN2

03604-0-070

APPLICATIONS

Broadband access

Broadband LAN

Communications (modems)

AD9863

Figure 1.

GENERAL DESCRIPTION

The AD9863 is a member of the MxFE family—a group of

integrated converters for the communications market. The

AD9863 integrates dual 12-bit analog-to-digital converters

(ADC) and dual 12-bit digital-to-analog converters (TxDAC®).

The AD9863 ADCs are optimized for ADC sampling of 50 MSPS

and less. The dual TxDACs operate at speeds up to 200 MHz

and include a bypassable 2× or 4× interpolation filter. The

AD9863 is optimized for high performance, low power, and

small form factor to provide a cost-effective solution for the

broadband communications market.

The AD9863 uses a single input clock pin (CLKIN) or two

independent clocks for the Tx path and the Rx path. The ADC

and TxDAC clocks are generated within a timing generation

block that provides user programmable options such as divide

circuits, PLL multipliers, and switches.

A flexible, bidirectional 24-bit I/O bus accommodates a variety

of custom digital back ends or open market DSPs.

In half-duplex systems, the interface supports 24-bit parallel

transfers or 12-bit interleaved transfers. In full-duplex systems,

the interface supports a 12-bit interleaved ADC bus and a

12-bit interleaved TxDAC bus. The flexible I/O bus reduces pin

count, also reducing the required package size on the AD9863

and the device to which it connects.

The AD9863 can use either mode pins or a serial programma-

ble interface (SPI) to configure the interface bus, operate the

ADC in a low power mode, configure the TxDAC interpolation

rate, and control ADC and TxDAC power-down. The SPI

provides more programmable options for both the TxDAC path

(for example, coarse and fine gain control and offset control for

channel matching) and the ADC path (for example, the internal

duty cycle stabilizer and twos complement data format).

The AD9863 is packaged in a 64-lead LFCSP (low profile, fine

pitched, chip scale package). The 64-lead LFCSP footprint is

only 9 mm × 9 mm and is less than 0.9 mm high, fitting into

such tightly spaced applications as PCMCIA cards.

Rev. B

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

AD9863

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ........................................................................... 2

Tx Path Specifications ...................................................................... 3

Rx Path Specifications ...................................................................... 4

Power Specifications ......................................................................... 5

Digital Specifications........................................................................ 5

Timing Specifications....................................................................... 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Data Sheet

Pin Configuration and Function Descriptions..............................8

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 18

System Block ............................................................................... 18

Rx Path Block .............................................................................. 18

Tx Path Block .............................................................................. 20

Digital Block................................................................................ 23

Programmable Registers............................................................ 33

Clock Distribution Block .......................................................... 36

Outline Dimensions ....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

4/2017—Rev. A to Rev. B

Changes to Figure 3 and Table 8 ..................................................... 8

Updated Outline Dimensions ....................................................... 42

Changes to Ordering Guide .......................................................... 42

4/2005—Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 40

11/2003—Revision 0: Initial Version

Rev. B | Page 2 of 40

AD9863BCPZRL-50 Related Products

	AD9863BCPZRL-50	AD9863BCPZ-50
Description	Analog to Digital Converters - ADC 12-Bit Mixed-Signal Front-End Processor	Analog to Digital Converters - ADC 12-Bit Mixed-Signal Front-End Processor
Product Category	Analog to Digital Converters - ADC	Analog to Digital Converters - ADC
Manufacturer	ADI	ADI
RoHS	Details	Details
Mounting Style	SMD/SMT	SMD/SMT
Package / Case	LFCSP-64	LFCSP-64
Resolution	12 bit	12 bit
Number of Channels	2 Channel	2 Channel
Sampling Rate	50 MS/s	50 MS/s
Input Type	Differential	Differential
Architecture	Pipeline	Pipeline
Reference Type	External, Internal	External, Internal
SNR - Signal to Noise Ratio	67 dB	67 dB
Maximum Operating Temperature	+ 85 C	+ 85 C
Minimum Operating Temperature	- 40 C	- 40 C
Packaging	Reel	Tray
Height	0.83 mm	0.83 mm
Length	9 mm	9 mm
Moisture Sensitive	Yes	Yes
Operating Supply Voltage	3.3 V	3.3 V
Product	Analog to Digital Converters	Analog to Digital Converters
Factory Pack Quantity	2500	260
Width	9 mm	9 mm

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