MCM63P531TQ8R datasheet, PDF - EEWORLD Datasheet

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MCM63P531TQ8R: Description32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM; Categorystorage storage; File Size167KB，16 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM63P531TQ8R Overview

32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P531TQ8R Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknow
ECCN code	3A991.B.2.B
Maximum access time	8 ns
JESD-30 code	R-PQFP-G100
length	20 mm
memory density	1048576 bi
Memory IC Type	CACHE SRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	100
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
organize	32KX32
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Advance Information

MCM63P531

32K x 32 Bit Pipelined BurstRAM™

Synchronous Fast Static RAM

The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide

a burstable, high performance, secondary cache for the 68K Family, PowerPC™,

and Pentium™ microprocessors. It is organized as 32K words of 32 bits each,

fabricated using high performance silicon gate CMOS technology. This device

integrates input registers, an output register, a 2–bit address counter, and high

speed SRAM onto a single monolithic circuit for reduced parts count in cache

data RAM applications. Synchronous design allows precise cycle control with the

use of an external clock (K). CMOS circuitry reduces the overall power consump-

tion of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output en-

able (G) and Linear Burst Order (

LBO

) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM63P531 (burst sequence op-

erates in linear or interleaved mode dependent upon state of LBO) and controlled

by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable SW are provided to allow writes to either individual bytes or to

all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

The MCM63P531 operates from a 3.3 V power supply, all inputs and outputs

are LVTTL compatible.

•

MCM63P531–4.5 = 4.5 ns access / 10 ns cycle

MCM63P531–7 = 7 ns access / 13.3 ns cycle

MCM63P531–8 = 8 ns access / 15 ns cycle

MCM63P531–9 = 9 ns access / 16.6 ns cycle

•

Single 3.3 V + 10%, – 5% Power Supply

•

ADSP, ADSC, and ADV Burst Control Pins

•

Selectable Burst Sequencing Order (Linear/Interleaved)

•

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

•

Sleep Mode (ZZ)

•

Intel PBSRAM 2.0 Compliant

•

Single–Cycle Deselect Timing

•

100 Pin TQFP Package

BurstRAM is a trademark of Motorola, Inc.

PowerPC is a trademark of IBM Corp.

Pentium is a trademark of Intel Corp.

This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.

TQ PACKAGE

TQFP

CASE 983A–01

6/21/96

Motorola, Inc. 1996

MOTOROLA FAST SRAM

MCM63P531

MCM63P531TQ8R Related Products

	MCM63P531TQ8R	MCM63P531TQ9R	MCM63P531TQ9	MCM63P531TQ8	MCM63P531TQ7R	MCM63P531TQ7	MCM63P531TQ4.5R	MCM63P531TQ4.5	MCM63P531
Description	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM	32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
Maker	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	-
package instruction	LQFP,	LQFP,	TQFP-100	TQFP-100	LQFP,	TQFP-100	LQFP,	LQFP, QFP100,.63X.87	-
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow	unknow	unknow	unknow	-
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	-
Maximum access time	8 ns	9 ns	9 ns	8 ns	7 ns	7 ns	4.5 ns	4.5 ns	-
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	-
length	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	-
memory density	1048576 bi	1048576 bi	1048576 bi	1048576 bi	1048576 bi	1048576 bi	1048576 bi	1048576 bi	-
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	-
memory width	32	32	32	32	32	32	32	32	-
Number of functions	1	1	1	1	1	1	1	1	-
Number of ports	1	1	1	1	1	1	1	1	-
Number of terminals	100	100	100	100	100	100	100	100	-
word count	32768 words	32768 words	32768 words	32768 words	32768 words	32768 words	32768 words	32768 words	-
character code	32000	32000	32000	32000	32000	32000	32000	32000	-
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-
organize	32KX32	32KX32	32KX32	32KX32	32KX32	32KX32	32KX32	32KX32	-
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	-
Exportable	YES	YES	YES	YES	YES	YES	YES	YES	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	-
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	-
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	-
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	-
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	-
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	-
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	-
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	-

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