PL600-27T
Low Power 3 Output XO
FEATURES
3 LVCMOS outputs with OE tri -state control
Low current consumption:
o
<4.5mA @ 27MHz, 3.3V
10 to 52MHz fundamental crystal input
1 to 100MHz reference clock input
Accepts both LVCMOS and sine wave inputs
Low phase noise (-130 dBc @ 10kHz offset)
Low jitter (RMS): 2.5ps period jitter
12mA drive capability at TTL output
1.8V to 3.3V operation
Available in GREEN/RoHS 8-pin SOP and 6-pin
SOT23 packages
PIN ASSIGNMENT
XIN/FIN
OE^
CLK1
GND
1
8
XOUT
CLK0
VDD
CLK2
PL600-27T
SOP-8L
2
3
4
7
6
5
^: Denotes internal Pull-up
DESCRIPTION
The PL600-27T is a low cost XO IC, designed to re-
place multiple XO solutions saving the cost and
board space of clock distribution buffers. In addition,
it provides among the lowest current on the market
for the 10MHz to 52MHz range. The PL600-27T ac-
cepts crystal and clock inputs from 10 to 52MHz
(fundamental resonant mode crystal) and provides
low phase noise (<-130dBc at 10kHz offset at
30MHz), and very low jitter (2.5 ps RMS period jitter)
outputs.
CLK1
GND
FIN
1
2
3
6
5
4
CLK2
VDD
CLK0
SOT23-6L
PL600-27T
BLOCK DIAGRAM
CLK0
XIN/FIN
XOUT
Xtal
Osc
CLK1
CLK2
OE
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 6/24/10 Page 1
PL600-27T
Low Power 3 Output XO
PIN DESCRIPTION
Name
XIN/FIN
OE
CLK1
GND
CLK2
VDD
CLK0
XOUT
Package Pin Number
SOP-8L
1
2
3
4
5
6
7
8
SOT23-6L
3
(FIN Only)
-
1
2
6
5
4
-
Type
I
I
O
P
O
P
O
I
Description
Crystal input (10MHz to 52MHz) or
Ref Clock input (1MHz to 100MHz)
Output Enable input. This pin has internal pull-up resistor.
All outputs will be tri -stated when low.
Output clock.
Ground.
Output clock.
Power supply.
Output clock.
Crystal output.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
-0.5
-0.5
-65
-40
MIN.
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
C
C
C
C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other
conditions above the operational limits noted in this specification is not implied.
*Operating temperature is guaranteed by design. Parts are
tested to commercial grade only.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 6/24/10 Page 2
PL600-27T
Low Power 3 Output XO
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Settling Time
Output Clock Rise/Fall Time
VDD sensitivity
Output Clock Duty Cycle
Short Circuit Current
3. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
4. DC Specifications
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
(at VDD = 3.3V)
Supply Current in Tri-State
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Output Drive Current
SYMBOL
I
DD
I
DD
V
DD
V
OH
V
OL
V
OHC
I
OH
= -12mA (3.3V)
I
OL
= 12mA (3.3V)
I
OH
= -4mA
At TTL level (3.3V)
V
DD
– 0.4
12
CONDITIONS
At 10MHz, Cload=15pF
At 27MHz, Cload=15pF
At 48MHz, Cload=15pF
Output disabled
1.62
2.4
0.4
MIN.
TYP.
2.0
4.0
7.0
MAX.
2.5
4.5
7.5
520
3.63
A
V
V
V
V
mA
mA
UNITS
CONDITIONS
With capacitive decoupling be-
tween V
DD
and GND.
30MHz @100Hz offset
30MHz @1kHz offset
30MHz @10kHz offset
30MHz @100kHz offset
30MHz @1MHz offset
MIN.
TYP.
2.1
-80
-110
-130
-138
-145
MAX.
2.5
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
LVCMOS or Sine Wave input
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
At power-up (V
DD
< 1.62V)
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Frequency vs. V
DD
+/- 10%
Measured @ 50% V
DD
0.8
45
50
50
CONDITIONS
MIN.
10
1
0.5
0.1
TYP.
MAX.
52
100
V
DD
V
DD
10
1.15
2.4
0.8
55
UNITS
MHz
MHz
Vpp
Vpp
ms
ns
ppm
%
mA
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 6/24/10 Page 3
PL600-27T
Low Power 3 Output XO
5. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Maximum Sustainable Drive Level
Operating Drive Level
C0 (for frequencies below 30MHz)
C0 (for frequencies above 30MHz)
ESR
R
S
50
5
4
30
SYMBOL
F
XIN
C
L (x ta l)
MIN.
10
8.5
200
TYP.
MAX.
52
UNITS
MHz
pF
W
W
pF
pF
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 6/24/10 Page 4
PL600-27T
Low Power 3 Output XO
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a pe rformance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper ter-
mination this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1
F
for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical LVCMOS termination
Place Series Resistor as close as possible to LVCMOS output
LVCMOS Output Buffer
( Typical buffer impedance 20
50 line
To LVCMOS Input
Series Resistor
Use value to match output
buffer impedance to 50
trace. Typical value 30
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
XIN
1
Cpt
8
Cpt
XOUT
CST
–
Series Capacitor, used to lower circuit load to match crystal load. Raises frequency
offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the
oscillator.
CPT
–
Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 6/24/10 Page 5
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